This week, PCI-standards consortium PCI-SIG (Special Interest Group) has ratified and released specifications for PCIe 4.0 Specification Version 1, uploading the documents to their PCI-SIG Specification Library. This marks the full release of PCIe 4.0, following up on June’s revision 0.9 specification publication. Doubling PCIe 3.0’s 8 GT/s (~1 GB/s) of bandwidth per lane, PCIe 4.0 offers a transfer rate of 16 GT/s with flexible lane width configurations, providing significant I/O performance benefits useful for storage, networking, and AI applications. At the same time, PCI-SIG has targeted Q2 2019 for releasing the finalized PCIe 5.0 specification, so PCIe 4.0 won't be quite as long-lived as PCIe 3.0 has been.

In context, PCI-SIG has previously kept to a four year cadence for PCIe 1.0 (2003), PCIe 2.0 (2006), and PCIe 3.0 (2010). In regards to the seven year delay, PCI-SIG noted that PCIe 3.0 provided sufficient bandwidth for some time before the developments and rising demands of AI compute workloads, PCIe NVMe and 3D XPoint storage, and networking speeds, particularly as 10GbE becomes more and more accessible to consumers. For compute GPUs, the bandwidth limitations of PCIe 3.0 had already driven NVIDIA in developing their proprietary NVLink interconnect. Consequently, with PCIe 4.0 and beyond, the PCI-SIG is looking to get back towards a more normal cadence, especially as they've now resolved some of the major technical hurdles in enabling faster transfer rates via the PCIe 4.0 standard.

The other aspect is the nature of the organization. PCI-SIG has almost 800 member companies, from which they annually elect a board of directors; for 2017-2018, the Board includes members from AMD, Intel, and NVIDIA. In developing and maintaining the open PCI specifications, members collaborate in committees and technical workgroups, submitting and reviewing specification changes. Part of PCI-SIG’s recent work is in streamlining in this process.

Once the specifications are finalized, members must have products pass interoperability and compliance tests at one of PCI-SIG’s many Compliance Workshops throughout the year, in order for the product to be added to the Integrators List, which OEMs and system integrators use in choosing hardware. For PCIe 4.0, PCI-SIG offered pre-publication Compliance Workshops for the first time, utilizing the earlier revision 0.9, but only at a preliminary “FYI Testing” level. For the rest of the year, PCI-SIG will offer PCIe 4.0 FYI Testing at Compliance Workshops; for the time being, PCIe 4.0 is not listed on either the official Compliance Program and Integrators List.

Like the previous PCIe iterations, PCIe 4.0 features backwards compatibility, and PCIe 1.x, 2.x, and 3.x cards will fit PCIe 4.0 slots and operate normally. PCIe 4.0 also maintains PCIe 3.0’s 128b/130b encoding, which will continue to be used in PCIe 5.0.

Among the other improvements, several features are more relevant for designers and developers than end users. As data rates increase, performance variation rises and signal integrity degrades. With that in mind, PCIe 4.0 brings lane margining at the PHY receiver, where the PCIe controller obtains electrical margin information of each PCIe lane in order to measure variation tolerance. PCIe 4.0 also has extended tags and credits, features that work together to mask latency and promote full bandwidth saturation. Other improvements include overall reduced system latency, I/O virtualization and platform integration, and added lanes/bandwitdth scalability, as well as enhanced Reliability, Availability, Serviceability (RAS) capabilities.

While gaming graphics cards are the most visible PCIe device to consumers, additional PCIe bandwidth overhead is unlikely to affect gaming performance, at least right away. However given the limited amount of PCIe bandwidth available with most consumer CPUs - just 16 general purpose lanes from the CPU with another 4 lanes for the chipset - this will also go a long way towards easing the pressure that the combination of GPUs, NVMe SSDs, and 10GigE networking can place on system I/O bandwidth. What may also be relevant is increased power capability from the secondary connectors, but at this point there are no further details, and a PCIe 4.0 Electromechanical Specification has not been disclosed.

As far as PCIe 4.0 vendor solutions go, Synopsys and Cadence, among others, are developing or offering 16GT/s PHYs and controllers, validation tools, and many other applications. IBM’s POWER9 feature PCIe 4.0 connections and Intel’s 10nm Falcon Mesa FPGA supports PCIe 4.0 as an IP block embedded via EMIB. Meanwhile, AMD have targeted 2020 for PCIe 4.0 support. But before products hit shelves, the PCIe 4.0 compliance and interoperability tests need to be finalized with both specifications and tools/procedures, and with the 32GT/s PCIe 5.0 fast-tracked to 2019, there may be very few, if any, consumer PCIe 4.0 devices. In any case, PCI-SIG only referred to the current PCIe 5.0 version 0.3, despite targeting Q4 2017 for version 0.5 at Hot Chips 2017.

PCI-SIG members may download the PCIe 4.0 specification for free at the Specification Library. Non-members may purchase a hard copy of the specification for $4,500.

Source: PCI-SIG

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  • bernstein - Thursday, October 26, 2017 - link

    cause it's getting cheap (because power consumption has finally come down) Reply
  • cdillon - Thursday, October 26, 2017 - link

    Fiber and DA (Direct-Attach copper) 10GbE SFP+ modules have been available for about 10 years now. It is specifically the 10GBASE-T SFP+ modules that have only been available for about a year. Reply
  • Notmyusualid - Friday, October 27, 2017 - link

    @ cdillon

    Yes, I was thinking, wait, what? 10GE SFPs/XFPs have been around for half my working lifetime...
    Reply
  • DanNeely - Friday, October 27, 2017 - link

    You're both looking at the subject with datacenter tinted glasses. Outside the enterprise world ethernet and RJ-45 are one and the same. SFP+, optical fiber, etc don't exist. Reply
  • Yojimbo - Friday, October 27, 2017 - link

    "In regards to the seven year delay, PCI-SIG noted that PCIe 3.0 provided sufficient bandwidth for some time before the developments and rising demands of AI compute workloads, PCIe NVMe and 3D XPoint storage, and networking speeds, particularly as 10GbE becomes more and more accessible to consumers."

    Or, maybe, put another way, the PCIe standard provided sufficient bandwidth until they stopped updating it; then it didn't. If PCIe 4.0 were released in 2014 there probably wouldn't have been such a problem of PCIe becoming a performance bottleneck for the "demands of AI compute workloads, PCIe NVMe and 3D XPoint storage, and networking speeds, particularly 10GbE".
    Reply
  • damianrobertjones - Friday, October 27, 2017 - link

    "Every 3 years..."

    Which means that a new product hits every 3 years, ensuring that the cycle of upgrading continues milking customers of their cash.
    Reply
  • mkaibear - Friday, October 27, 2017 - link

    Yeah, it's really really annoying that the PCI-SIG can force people to spend money on new hardware. Such a shame we don't have any choice over whether or not to upgrade. Reply
  • Yojimbo - Friday, October 27, 2017 - link

    He wants a new processor that works with the old surrounding technology. But, because of the way large scale semiconductor design and manufacturing works, and because significant markets need these new memory, bus, and networking technologies (including the fastest growing and highest margins ones), consumers can't afford to lag behind the advancing standards (otherwise all the processors cost more because the market becomes very segmented). I am guessing Intel makes more money on their CPUs than on their chip sets. I don't think they are trying to force people to upgrade more components of their system than they might otherwise want to. They are just keeping their platform up to date. And if they didn't do that, so many people would complain "why can't I have X new technology that I want, just like Y users get" such as NVMe SSDs or DDR4 DRAM or PCIe 4.0. Reply
  • name99 - Saturday, October 28, 2017 - link

    But a new processor DOES work with "the old surrounding technology".
    Most of the people in the world do NOT upgrade their external HDs, or wifi base stations, or ethernet switches, or screens, or ..., when they buy a new PC.
    They replace those surrounding technology pieces when they break, and not a day sooner.

    I don't understand his complaint, and I don't understand your attempt to justify it.
    Reply
  • Yojimbo - Sunday, October 29, 2017 - link

    I think the reason you can't understand either of us is because you do not have the relevant technology in mind. The article concerns the system bus, not peripherals. So, it makes sense that op's complaint is about the system bus. Since a new system bus on the market doesn't force anyone to buy a new processor or new peripherals, I can only imagine his complaint is that he has to buy a new motherboard when he buys a new processor. The peripherals will still work regardless, as you point out. You are correct in that that partially refutes his point that they are forcing customers to upgrade, milking cash. But, in general, when one gets a new processor one will probably need a new motherboard, and perhaps new RAM.

    The memory controllers are integrated into the processor die. PCIe controllers are integrated into the processing die. I believe it's not easy to get the new technology to work with the old pin layout. It certainly reduces the flexibility in the engineering to try. Most of Intel's customers move to a new platform when they buy a new processor, because they rely on various parts of the improved ecosystem, or because they buy new computers each time and don't upgrade. The number of people truly interested in buying a new processor and keeping their old motherboard is low. Probably mostly hobbyists/enthusiasts. It doesn't make sense for Intel to change their engineering work flow for a small group of customers.
    Reply

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