During a time of increased competitor activity, Intel has decided to disclose some of the high level details surrounding its next generation consumer processor, known as Rocket Lake or Intel’s 11th Gen Core. The new processor family is due in the market in the first quarter of 2021, and is expected to share a socket and motherboard compatibility with the current 10th Gen Comet Lake processors, providing an upgrade path even for those with a Core i9-10900K, Intel’s highest performing desktop processor to date. New 500-series motherboards are also expected to be available.

The new Rocket Lake-S silicon or SoC is going to be known as ‘Cypress Cove’. Intel confuses itself in the press release compared to the PDF presentation, as the press release dictates that this isn’t the core – it specifically states that the core microarchitecture is Ice Lake (Sunny Cove). However the presentation PDF says Cypress Cove is the core. In this instance, to be clear, Sunny Cove and Cypress Cove are set to be practically identical, however Sunny Cove is on 10nm and Cypress Cove is the back-ported variant on 14nm.

Paired with these cores will be the Tiger Lake graphics architecture, known as Xe-LP, which is also being backported from 10nm to 14nm for this product. The combined 14nm representation of Ice Lake cores and Xe-LP graphics is what is going to be known as Rocket Lake, (at least one of) the SoC(s) of the 11th Gen Core family.

With the new processors, Intel is targeting a raw instruction-per-clock uplift in the double digit range, which would be similar to the uplift we saw moving from Comet Lake to Intel’s Ice Lake mobile processors. Because of the node difference, the exact IPC change is likely to be lower than what we’ve seen before, but 10%+ is still highly respectable, especially if Intel is also able to maintain the high frequency it has achieved with the current generation of Comet Lake.

One of the benefits of moving to a back-ported Sunny Cove core will be the inclusion of the AVX-512 vector acceleration unit in Cypress Cove. This enables Intel to enable its library of Deep Learning Boost technologies for AI and ML acceleration, including support for Vector Neural Network Instructions (VNNI), finally bringing AVX-512 to the desktop platform.

However, to mix and match the right combination of core count, graphics, and AVX-512 for die size/yield/cost, it appears that Rocket Lake-S will only offer a maximum of eight cores in its largest configuration. Within the press release PDF, Intel stated that the current silicon as tested is rated for 125 W TDP, with a top turbo boost of 250 W, which matches what we see on the Core i9-10900K already. There’s no escaping the performance-per-watt characteristics of the process node, which indicates that Intel might find hitting those high frequencies a little easier with fewer cores to deal with. Intel is also promoting new overclocking tools with Rocket Lake, however did not go into details.

Another feature that Intel has disclosed with Rocket Lake is the move to PCIe Gen 4.0 on the processor, with up to 20 lanes available. These are likely to be split into one x16 for graphics and one x4 for storage on most motherboards, and this aligns with what we’ve seen on the latest generation of Intel Z490 motherboards, some of which have already promoted support for PCIe 4.0 ‘on future Intel processors’. This means Rocket Lake. Intel also mentions that the memory controller now supports up to DDR4-3200, however the projected performance numbers were done with DDR4-2933 memory.

On the graphics side, moving to the Xe-LP graphics architecture is going to be a big uplift in graphics performance, with Intel suggesting a 50% improvement over current Comet Lake integrated graphics. It is worth noting here in the slide that Intel mentions ‘UHD Graphics ft Xe Graphics Architecture’ – this would perhaps point to a scaled down version of Xe compared to Tiger Lake. I’m fully expecting to see only 32 EUs here, as a balance between die area, power, and performance. In the fine print it suggests that there will be some versions of Rocket Lake without the integrated graphics enabled, similar to the F processors we see on the market today.

That being said, for those units with integrated graphics, Intel is promoting new media encoders and display resolution support, with up to 4K60 12-bit for 4:4:4 HEVC and VP9, or up to 4K60 with 10-bit 4:2:0 AV1, showcasing AV1 support for mainstream processors. Display resolution support has also increased, with up to three 4K60 displays or two 5K60 displays, supporting DP 1.4a (with HBR3) and HDMI 2.0b.

This was an unexpected news announcement this morning - speaking to peers it all seems to be a bit of a surprise - perhaps even for the PR teams, given that the system configurations as 'projected' in the slide above is dated 6th August, almost 3 months ago. It will be interesting to hear if Intel will disclose more details ahead of launch.

Source: Intel

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  • Spunjji - Friday, October 30, 2020 - link

    That's a nope
  • AntonErtl - Friday, October 30, 2020 - link

    Given how much time they needed to port Sunny Cove to 14nm, it's interesting that they managed to do the very recent Xe graphics in 14nm. This means that for Xe graphics they either use a more automatic approach for the last process-specific steps of designing such a thing than for Sunny Cove, or they did these steps almost in parallel for 10nm and 14nm for Xe graphics. My gess is that it's the former.

    Why Sunny Cove and not Willow Cove, i.e. why a smaller L2 cache? My guess is area. Why only 8 cores? My guess is area; power would just lower the base clock, which is not that important to most buyers. Why AVX-512? It's part of Sunny Cove and a USP for Intel; they already had it in Cannon Lake and Skylake-SP; I am actually surprised that AMD has not implemented it yet (even though it's not used in much software).
  • AdrianBc - Friday, October 30, 2020 - link

    It is not clear whether they have back-ported Xe graphics to 14 nm.

    All the previous rumors about Rocket Lake said that it will be composed of 2 chips, inside the package, a 14-nm back-ported CPU and a 10-nm Xe GPU.
  • Spunjji - Friday, October 30, 2020 - link

    That would just leave even more questions, like, how does that 10nm GPU access memory?

    Honestly it's way more plausible that they did an automated hack-job on 32EU Xe than they figured out MCM for GPU connected to a CPU with an on-board memory controller and... just decided not to tell anyone.
  • AdrianBc - Friday, October 30, 2020 - link

    Intel has already done CPU + GPU combinations in a single package, the Kaby Lake G processors, which included an AMD Radeon GPU.
    That had more constraints, because they had to use PCIe links, as only that was compatible with the AMD GPU. With their own GPU, they would have been free to implement some custom communication protocol, maybe more suitable for the task.
  • Spunjji - Monday, November 2, 2020 - link

    Kaby Lake G didn't share a memory controller, and it's not a relevant comparison. The better one would have been Arrandale, Intel's first go at on-package Northbridge and graphics. It worked because the GPU was weak and sat next to the memory controller, which was already decoupled from the CPU because they hadn't integrated it into the CPU core design yet.

    Seriously, the GPU on Rocket Lake is integrated at 14nm. No need to take my word for it though, you'll find out in about 4 months when it actually becomes relevant.
  • Santoval - Friday, October 30, 2020 - link

    Your guesses appear to be correct. Smaller die size means higher yields and thus lower costs. Intel do not normally have a yield issue with their hyper-mature 14nm process node, but I have no idea whether backporting a new CPU and GPU μarch affected their yields at 14nm. Maybe they just wanted to play it safe since this is the first time they tried that.
  • DannyH246 - Friday, October 30, 2020 - link

    Oh WOW!!!! Another "look what we'll have in the future" article from Intel.

    Definitely definitely do not buy anything until this amazing architecture is released.
  • Toadster - Friday, October 30, 2020 - link

    interesting that the CML test setup used the 760p SSD and RKL used 660p https://ark.intel.com/content/www/us/en/ark/compar...
  • Golgatha777 - Friday, October 30, 2020 - link

    4 more PCIe lanes will help with a single M.2 SSD, but is Intel going to up the bandwidth of the DMI connection past 3.93GB/s in case users might want more than one M.2 SSD in the system?


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