Medfield: Intel in a Smartphone

I touched on this before but there were a number of reasons we never saw Moorestown in a smartphone. One part of the problem was the number of packages required to implement the platform, the other was that it simply lacked some of the things that smartphone OEMs implicitly expect to live on an SoC. The internal Intel guidance was that Moorestown required 2 packages to implement (Lincroft and Langwell), and in addition to those two you needed an external PMIC and DRAM. There wasn’t support for PoP memory, only external LPDDR1, and there was only support for 5 MP camera and 720p encode.

Medfield builds in every way on top of this by delivering a bona fide SoC with PoP LPDDR2 (2 x 32 bit support), improved ISP from Intel’s Silicon Hive acquisition, video encode and decode blocks from Imagination, SGX 540 graphics at 400 MHz, additional I/O, and an external Avatele Passage PMIC (Intel calls this an MSIC). The result is a platform that looks to an OEM like any of the other competitors - it’s a combination of SoC, PMIC, and some PoP LPDDR2, as opposed to the previous solution which required two additional external packages. Intel has a few slides online about this evolution and how things have moved inside the single Medfield package, and the result again is something that finally looks like any one of countless ARM-based SoCs.

The specific part inside the X900 is an Atom Z2460 32nm SoC (the platform is Medfield, Penwell is the SoC, and the CPU inside is a Saltwell), and inside a Penwell is the Atom Saltwell core running at up to 1.6 GHz with 512KB of L2 cache, a PowerVR SGX 540 GPU at 400 MHz, and a dual channel LPDDR2 memory interface. Anand has already written about the CPU architecture itself pretty comprehensively, and how it compares to ARM’s Cortex A9 and A15 designs. The long and short of it is that Saltwell is still a dual-issue, in-order core with Hyper-Threading support. There’s a 16 stage integer pipeline, no dedicated integer multiply or divide units (they’re shared with the floating point hardware), and in addition to the 512KB L2 cache there’s a separate 256KB SRAM which is lower power and on its own voltage plane. When Saltwell goes into its deepest sleep state, the CPU state and some L2 cache data gets parked here, allowing the CPU voltage to be lowered even more than the SRAM voltage. As expected, with Hyper-Threading the OS sees two logical cores to execute tasks on.

The other interesting thing is support for EIST and additional C states when the device is idle. Dynamic CPU clocks through the linux governor is something absolutely critical for getting a smartphone with acceptable battery life. What’s interesting here is that Penwell’s advertised dynamic range is between 100 MHz and 1.6 GHz with fine grained 100 MHz increments between, in addition to the C6 state where CPU state data is saved in the on-SoC low power SRAM and the platform is basically suspended (deep sleep).

However, the Android governor onboard the X900 only includes a few steps between 600 MHz and the maximum 1.6 GHz burst clock, in addition to C6. You can see this either by inspecting the governor’s available scaling frequencies:

$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
1600000 1400000 1200000 900000 600000 
$ cat time_in_state
1600000 233495
1400000 12304
1200000 19780
900000 25801
600000 5306262

Or by using an Android application which inspects exactly this data. I spent a day with the Medfield phone in my pocket and made a note of capturing what the state data was after the day’s end, and the CPU does indeed go into C6 while idle and in the pocket, and spend a lot of time at the minimum 600 MHz clock with some bursts to 1.6 GHz when I’m doing things.

 

The reality is that most of the smartphone’s time is really spent idling, waking up only to watch some DRX slots or process background tasks. It is curious to me however that Intel isn’t implementing their Ultra-LFM modes between 100 and 600 MHz - it’s possible there’s no voltage scaling below 600 MHz which in turn doesn’t make it worth jumping into these lower clocks quite yet.

Depending on the device’s thermals, Intel’s governor will select between those available frequencies. There actually are four thermal zones in the device, on the back, front, baseband, and SoC itself. The SoC can go up to 90C before you get throttled (which is pretty typical for Intel CPUs), 75 C on the back, 64 C on the front, and 80 C on the modem. Those sound high but aren’t out of the ordinary for some of the other SoCs I’ve seen who have similar thermal management. In addition, if the platform gets too hot, the display brightness will be clamped to 50%.

I have to admit that I did see the display brightness get clamped once as shown above, but only once during a period where I was running the display at 100% brightness and maxing out the CPU. The bottom back of the X900 can indeed get warm, but nothing inordinate or near the thermals that are set in the software management.

Finally, Saltwell supports the same instruction set as Core 2, including SSE3 and Intel 64. We can check this by looking at the CPU flags from cpu_info as well:

processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 39
model name : Intel(R) Atom(TM) CPU Z2460  @ 1.60GHz
stepping : 2
cpu MHz : 600.000
cache size : 512 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 1
apicid : 0
initial apicid : 0
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx constant_tsc arch_perfmon pebs bts nonstop_tsc aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 xtpr pdcm movbe lahf_lm arat tpr_shadow vnmi flexpriority
bogomips : 3194.88
clflush size : 64
cache_alignment : 64
address sizes : 32 bits physical, 32 bits virtual
power management:

The rest of the Medfield platform we’ll talk about in the appropriate sections, but the big takeaway is that Intel finally has a real x86 SoC for smartphones and tablets. In addition to the Z2460 that we’re looking at in the X900, Intel has two other SKUs which round out the high end and low end. At the low end is the Z2000 which is functionally identical to the Z2460 but with a maximum CPU clock of 1.0 GHz, no HT, and an SGX 540 clock of 320 MHz, and the Z2580 which is clearly targeted at Windows 8 tablets with two Saltwell cores clocked up to 1.8 GHz, and PowerVR SGX544MP2 graphics at 533 MHz for Direct3D 9_3 compliance.

The Road to Medfield, and The Device Android on x86 and Binary Translation
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  • superPC - Thursday, April 26, 2012 - link

    Well this atom only has 1/4 of conroe dual core transistor count right now. a move to 22nm could bring conroe level performance.
  • Khato - Thursday, April 26, 2012 - link

    Remember, conroe class performance simply indicates a general IPC level. I don't expect something on par with an E8600, more like a SU9600. It's quite feasible on the 22nm LP process, and actually is roughly in-line with the one Atom performance roadmap from awhile ago.
  • extide - Wednesday, April 25, 2012 - link

    That wont be happening for a while, but from what I have heard 2013 will bring us a second gen (out-of-order) atom on a mature 22nm process. We should see 2Ghz+ clockspeeds and 2 cores, plus a healthy IPC boost. This is going to be an exciting battle to watch, the old Intel vs AMD gig is kind of stale, so its awesome to see a real challenge for Intel again!
  • A5 - Wednesday, April 25, 2012 - link

    ULV Haswell will have a TDP an order of magnitude too high for a phone form factor. Tablets, maybe.
  • MonkeyPaw - Wednesday, April 25, 2012 - link

    "We waited years for Intel's first smartphone, now the question is how long do we have to wait for the first irresistable one?"

    It wont matter. Intel will dump millions into advertising, and every single phone maker will have ads for their new x86 phones, ending with the usual Intel chorus.
  • dougys - Wednesday, April 25, 2012 - link

    I read somewhere else a few weeks back that the iPhone 5 could have Intel Inside. However, something else I read suggested that if they were to do this all the apps would have to be re-written... Does anyone have any thoughts/insight?
  • tipoo - Wednesday, April 25, 2012 - link

    Apple has a few architecture changes under its belt, but I very much doubt it, not for this chip. Apple bought chip design companies and spends more on internal chip design year after year for good reason.

    Not sure about iOS compatibility but this chip can run any Android apps just fine as the article points out through binary translation, I think Android apps use Java and iOS uses C++ though so I'm not sure if that would still work.

    If Apple was to go to an outside design for its chips (which I highly doubt it will) I'd hope it would be for Qualcomm, Krait is amazing.
  • dcollins - Wednesday, April 25, 2012 - link

    Apple will not move to an Intel chip anytime soon because they have been very successful in designing their own SoC. Just look at the battery life benchmarks: Apple crushes everyone in Hours/Watt*Hour. Plus, doing it in house gives them more flexibility on the overall design of their boards.

    There is a small chance of Intel manufacturing chips for Apple, but that is a long shot as well. Chips manufactured on Intel's 22nm 3d gate process would be incompatible with chips produced on competing 28nm processes (different physical size) and Apple is traditionally opposed to single sourcing crucial components.
  • tipoo - Wednesday, April 25, 2012 - link

    Why does the GN get worse flash performance than the Nexus S and even Nexus One? That isn't a resolution dependant test, right?

    I'm also curious why the dual core Atrix barely does better than the single core Nexus S in Vellamo, was that just a bad SoC design or is it because it runs an older OS?
  • tipoo - Wednesday, April 25, 2012 - link

    I also just got 915 on my Nexus S rather than 622, but I'm using an unofficial Cyanogenmod 9 build from XDA forums.

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