The Cortex-X2: More Performance, Deeper OoO

We first start off with the Cortex-X2, successor to last year’s Cortex-X1. The X1 marked the first in a new IP line-up from Arm which diverged its “big” core offering into two different IP lines, with the Cortex-A sibling continuing Arm’s original design philosophy of PPA, while the X-cores are allowed to grow in size and power in order to achieve much higher performance points.

The Cortex-X2 continues this philosophy, and further grows the performance and power gap between it and its “middle” sibling, the Cortex-A710. I also noticed that throughout Arm’s presentation there were a lot more mentions of having the Cortex-X2 being used in larger-screen compute devices and form-factors such as laptops, so it might very well be an indication of the company that some of its customers will be using the X2 more predominantly in such designs for this generation.

From an architectural standpoint the X2 is naturally different from the X1, thanks in large part to its support for Armv9 and all of the security and related ISA platform advancements that come with the new re-baselining of the architecture.

As noted in the introduction, the Cortex-X2 is also a 64-bit only core which only supports AArch64 execution, even in PL0 user mode applications. From a microarchitectural standpoint this is interesting as it means Arm will have been able to kick out some cruft in the design. However as the design is a continuation of the Austin family of processors, I do wonder if we’ll see more benefits of this deprecation in future “clean-sheet” big cores designs, where AArch64-only was designed from the get-go. This, in fact, is something that's already happening in other members of Arm's CPU cores, as the new little core Cortex-A510 was designed sans-AArch32.

Starting off with the front-end, in general, Arm has continued to try to improve what it considers the most important aspect of the microarchitecture: branch prediction. This includes continuing to run the branch resolution in a decoupled way from the fetch stages in order to being able to have these functional blocks be able to run ahead of the rest of the core in case of mispredicts and minimize branch bubbles. Arm generally doesn’t like to talk too much details about what exactly they’ve changed here in terms of their predictors, but promises a notable improvement in terms of branch prediction accuracy for the new X2 and A710 cores, effectively reducing the MPKI (Misses per kilo instructions) metric for a very wide range of workloads.

The new core overall reduces its pipeline length from 11 cycles to 10 cycles as Arm has been able to reduce the dispatch stages from 2-cycles to 1-cycle. It’s to be noted that we have to differentiate the pipeline cycles from the mispredict penalties, the latter had already been reduced to 10 cycles in most circumstances in the Cortex-A77 design. Removing a pipeline stage is generally a rather large change, particularly given Arm’s target of maintaining frequency capabilities of the core. This design change did incur some more complex engineering and had area and power costs; but despite that, as Arm explains in, cutting a pipeline stage still offered a larger return-on-investment when it came to the performance benefits, and was thus very much worth it.

The core also increases its out-of-order capabilities, increasing the ROB (reorder buffer) by 30% from 224 entries to 288 entries this generation. The effective figure is actually a little bit higher still, as in cases of compression and instruction bundling there are essentially more than 288 entries being stored. Arm says there’s also more instruction fusion cases being facilitated this generation.

On the back-end of the core, the big new change is on the part of the FP/ASIMD pipelines which are now SVE2-capable. In the mobile space, the SVE vector length will continue to be 128b and essentially the new X2 core features similar throughput characteristics to the X1’s 4x FP/NEON pipelines. The choice of 128b vectors instead of something higher is due to the requirement to have homogenous architectural feature-sets amongst big.LITTLE designs as you cannot mix different vector length microarchitectures in the same SoC in a seamless fashion.

On the back-end, the Cortex-X2 continues to focus on increasing MLP (memory level parallelism) by increasing the load-store windows and structure sizes by 33%. Arm here employs several structures and generally doesn’t go into detail about exactly which queues have been extended, but once we get our hands on X2 systems we’ll be likely be able to measure this. The L1 dTLB has grown from 40 entries to 48 entries, and as with every generation, Arm has also improved their prefetchers, increasing accuracies and coverage.

One prefetcher that surprised us in the Cortex-X1 and A78 earlier this year when we first tested new generation devices was a temporal prefetcher – the first of its kind that we’re aware of in the industry. This is able to latch onto arbitrary repeated memory patterns and recognize new iterations in memory accesses, being able to smartly prefetch the whole pattern up to a certain depth (we estimate a 32-64MB window). Arm states that this coverage is now further increased, as well as the accuracy – though again the details we’ll only able to see once we get our hands on silicon.

In terms of IPC improvements, this year’s figures are quoted to reach +16% in SPECint2006 at ISO frequency. The issue with this metric (and which applies to all of Arm’s figures today) is that Arm is comparing an 8MB L3 cache design to a 4MB L3 design, so I expect a larger chunk of that +16% figure to be due to the larger cache rather than the core IPC improvements themselves.

For their part, Arm is reiterating that they're expecting 8MB L3 designs for next year’s X2 SoCs – and thus this +16% figure is realistic and is what users should see in actual implementations. But with that said, we had the same discussion last year in regards to Arm expecting 8MB L3 caches for X1 SoCs, which didn't happen for either the Exynos 2100 nor the Snapdragon 888. So we'll just have to wait and see what cache sizes the flagship commercial SoCs end up going with.

In terms of the performance and power curve, the new X2 core extends itself ahead of the X1 curve in both metrics. The +16% performance figure in terms of the peak performance points, though it does come at a cost of higher power consumption.

Generally, this is a bit worrying in context of what we’re seeing in the market right now when it comes to process node choices from vendors. We’ve seen that Samsung’s 5LPE node used by Qualcomm and S.LSI in the Snapdragon 888 and Exynos 2100 has under-delivered in terms of performance and power efficiency, and I generally consider both big cores' power consumption to be at a higher bound limit when it comes to thermals. I expect Qualcomm to stick with Samsung foundry in the next generation, so I am admittedly pessimistic in regards to power improvements in whichever node the next flagship SoCs come in (be it 5LPP or 4LPP). It could well be plausible that we wouldn’t see the full +16% improvement in actual SoCs next year.

2022 Generation: Moving Towards Armv9 The Cortex-A710: More Performance with More Efficiency
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  • Spunjji - Thursday, May 27, 2021 - link

    Comments saying "x86 is dead" are just as daft as the comments declaring that ARM will never be a threat to x86. Reply
  • mode_13h - Tuesday, May 25, 2021 - link

    What a terrible naming scheme!

    If they didn't want to just start from a blank slate, they should've gone on to letters. So, A7A and A5A.

    Also, given that the X-cores are typically going to be paired with their cousin A-series core, the naming scheme should reflect that relationship. So, maybe the X1 should've been the X78 and the X2 could be the X710 or X7A.
    Reply
  • mode_13h - Tuesday, May 25, 2021 - link

    Also, why skip 9? A59 and A79 would be a great mnemonic for the first mobile cores to be ARMv9! Reply
  • nandnandnand - Tuesday, May 25, 2021 - link

    I'm fine with the naming scheme.

    For the Cortex-X line, they can just do X1, X2, X3, X4... X-cetera.

    For these new ones, A710 and A510 are the baseline, and they can put out A720, A525, or whatever until they run it up to A799. That could take over a decade if they don't increment the numbers so much. The '7' and '5' let you know these are related to the A78/A55, and the 3 digits lets you know it's part of the brave new world of ARMv9.
    Reply
  • mode_13h - Tuesday, May 25, 2021 - link

    > they can put out A720

    That could potentially create some confusion about the relationship between A72 and A720.

    > 3 digits lets you know it's part of the brave new world of ARMv9.

    Okay, so create a new numbering scheme! No need to piggy back off the old one, if it's "a brave new world", right?
    Reply
  • phoenix_rizzen - Tuesday, May 25, 2021 - link

    Would have been a good time to pick new letters. Leave Cortex-A, Cortex-X, Cortex-M etc for Armv8.x.

    Even better, drop the Cortex name, and pick something new for Armv9-based cores.

    X, Y, Z would have been nice for big, middle, little cores.

    Ah well, marketing-droids will do what marketing-droids do. :D
    Reply
  • mode_13h - Tuesday, May 25, 2021 - link

    Also, A79 would line up nicely with being the last generation of this microarchitecture family.

    Then, maybe the "Sophia" cores could start a new numbering series.
    Reply
  • GeoffreyA - Thursday, May 27, 2021 - link

    "What a terrible naming scheme!"

    They should battle it out with Intel's Marketing arm to see who's the best in the field of naming.
    Reply
  • eastcoast_pete - Tuesday, May 25, 2021 - link

    Disappointed in the design choice of the new LITTLE cores. I have the strong suspicion that the IPC comparison of the 510 LITTLE core to the A73 (the 510 getting close to the A73) is with one 510 core per complex, maximal cache and cache bandwidth etc, which, of course, is highly theoretical. After all, the 510s are designed to come in pairs sharing resources for a reason. I am underwhelmed by this design, ARM's own power/perf curves show very little if any difference to A55 until one gets to the high end of the power curve, at which point the 710 big cores would have taken over. Unfortunately, Apple's power/perf crown for efficiency cores remains quite and comfortably safe. As an Android user, however, I remain stuck with ARM's designs, as none of the design houses (QC, Samsung) is even attempting custom core designs for smartphone SoCs. We are seeing the downside of a monopoly here Reply
  • mode_13h - Tuesday, May 25, 2021 - link

    > I remain stuck with ARM's designs, as none of the design houses (QC, Samsung)
    > is even attempting custom core designs for smartphone SoCs.

    Qualcomm is saying they're using their Nuvia acquisition to make new mobile cores.
    Reply

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