The Cortex-X2: More Performance, Deeper OoO

We first start off with the Cortex-X2, successor to last year’s Cortex-X1. The X1 marked the first in a new IP line-up from Arm which diverged its “big” core offering into two different IP lines, with the Cortex-A sibling continuing Arm’s original design philosophy of PPA, while the X-cores are allowed to grow in size and power in order to achieve much higher performance points.

The Cortex-X2 continues this philosophy, and further grows the performance and power gap between it and its “middle” sibling, the Cortex-A710. I also noticed that throughout Arm’s presentation there were a lot more mentions of having the Cortex-X2 being used in larger-screen compute devices and form-factors such as laptops, so it might very well be an indication of the company that some of its customers will be using the X2 more predominantly in such designs for this generation.

From an architectural standpoint the X2 is naturally different from the X1, thanks in large part to its support for Armv9 and all of the security and related ISA platform advancements that come with the new re-baselining of the architecture.

As noted in the introduction, the Cortex-X2 is also a 64-bit only core which only supports AArch64 execution, even in PL0 user mode applications. From a microarchitectural standpoint this is interesting as it means Arm will have been able to kick out some cruft in the design. However as the design is a continuation of the Austin family of processors, I do wonder if we’ll see more benefits of this deprecation in future “clean-sheet” big cores designs, where AArch64-only was designed from the get-go. This, in fact, is something that's already happening in other members of Arm's CPU cores, as the new little core Cortex-A510 was designed sans-AArch32.

Starting off with the front-end, in general, Arm has continued to try to improve what it considers the most important aspect of the microarchitecture: branch prediction. This includes continuing to run the branch resolution in a decoupled way from the fetch stages in order to being able to have these functional blocks be able to run ahead of the rest of the core in case of mispredicts and minimize branch bubbles. Arm generally doesn’t like to talk too much details about what exactly they’ve changed here in terms of their predictors, but promises a notable improvement in terms of branch prediction accuracy for the new X2 and A710 cores, effectively reducing the MPKI (Misses per kilo instructions) metric for a very wide range of workloads.

The new core overall reduces its pipeline length from 11 cycles to 10 cycles as Arm has been able to reduce the dispatch stages from 2-cycles to 1-cycle. It’s to be noted that we have to differentiate the pipeline cycles from the mispredict penalties, the latter had already been reduced to 10 cycles in most circumstances in the Cortex-A77 design. Removing a pipeline stage is generally a rather large change, particularly given Arm’s target of maintaining frequency capabilities of the core. This design change did incur some more complex engineering and had area and power costs; but despite that, as Arm explains in, cutting a pipeline stage still offered a larger return-on-investment when it came to the performance benefits, and was thus very much worth it.

The core also increases its out-of-order capabilities, increasing the ROB (reorder buffer) by 30% from 224 entries to 288 entries this generation. The effective figure is actually a little bit higher still, as in cases of compression and instruction bundling there are essentially more than 288 entries being stored. Arm says there’s also more instruction fusion cases being facilitated this generation.

On the back-end of the core, the big new change is on the part of the FP/ASIMD pipelines which are now SVE2-capable. In the mobile space, the SVE vector length will continue to be 128b and essentially the new X2 core features similar throughput characteristics to the X1’s 4x FP/NEON pipelines. The choice of 128b vectors instead of something higher is due to the requirement to have homogenous architectural feature-sets amongst big.LITTLE designs as you cannot mix different vector length microarchitectures in the same SoC in a seamless fashion.

On the back-end, the Cortex-X2 continues to focus on increasing MLP (memory level parallelism) by increasing the load-store windows and structure sizes by 33%. Arm here employs several structures and generally doesn’t go into detail about exactly which queues have been extended, but once we get our hands on X2 systems we’ll be likely be able to measure this. The L1 dTLB has grown from 40 entries to 48 entries, and as with every generation, Arm has also improved their prefetchers, increasing accuracies and coverage.

One prefetcher that surprised us in the Cortex-X1 and A78 earlier this year when we first tested new generation devices was a temporal prefetcher – the first of its kind that we’re aware of in the industry. This is able to latch onto arbitrary repeated memory patterns and recognize new iterations in memory accesses, being able to smartly prefetch the whole pattern up to a certain depth (we estimate a 32-64MB window). Arm states that this coverage is now further increased, as well as the accuracy – though again the details we’ll only able to see once we get our hands on silicon.

In terms of IPC improvements, this year’s figures are quoted to reach +16% in SPECint2006 at ISO frequency. The issue with this metric (and which applies to all of Arm’s figures today) is that Arm is comparing an 8MB L3 cache design to a 4MB L3 design, so I expect a larger chunk of that +16% figure to be due to the larger cache rather than the core IPC improvements themselves.

For their part, Arm is reiterating that they're expecting 8MB L3 designs for next year’s X2 SoCs – and thus this +16% figure is realistic and is what users should see in actual implementations. But with that said, we had the same discussion last year in regards to Arm expecting 8MB L3 caches for X1 SoCs, which didn't happen for either the Exynos 2100 nor the Snapdragon 888. So we'll just have to wait and see what cache sizes the flagship commercial SoCs end up going with.

In terms of the performance and power curve, the new X2 core extends itself ahead of the X1 curve in both metrics. The +16% performance figure in terms of the peak performance points, though it does come at a cost of higher power consumption.

Generally, this is a bit worrying in context of what we’re seeing in the market right now when it comes to process node choices from vendors. We’ve seen that Samsung’s 5LPE node used by Qualcomm and S.LSI in the Snapdragon 888 and Exynos 2100 has under-delivered in terms of performance and power efficiency, and I generally consider both big cores' power consumption to be at a higher bound limit when it comes to thermals. I expect Qualcomm to stick with Samsung foundry in the next generation, so I am admittedly pessimistic in regards to power improvements in whichever node the next flagship SoCs come in (be it 5LPP or 4LPP). It could well be plausible that we wouldn’t see the full +16% improvement in actual SoCs next year.

2022 Generation: Moving Towards Armv9 The Cortex-A710: More Performance with More Efficiency
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  • ikjadoon - Tuesday, May 25, 2021 - link

    Fair; I'll take a K12 successor as recompense.

    The business side is good context I forgot, but now in 2021, AMD is in much better straits and surely K12's successor is worth a shot.

    https://www.anandtech.com/show/7990/amd-announces-...

    Surely there were great ideas in Keller's work, their team's work, in their post-Styx designs

    AMD might find a lot of benefit in preparing an Arm roadmap. What's to stop consoles, laptops, desktops from switching to Arm, from AMD"s financial perspective? Hopefully, they have clear eyes on x86's relevance to both consumers & businesses. AMD has a knack for fighting back, so I hope the build on their financial momentum.
    Reply
  • TheinsanegamerN - Wednesday, May 26, 2021 - link

    Compatibility, performance, and existence.

    ARM brings compatibility issues with previously existing software. Emulation wont work 100%,a nd compatibility with existing hardware is a minefield

    With that emulation/compatibility layer comes performance degregations. Sometimes it may not be so bad, other times it will be horrendous. The overall software market is not as tightly controlled as apple's walled garden approach.

    And finally, existence. There is currently no high performance ARM processor in existence. Show me a desktop ARM process ro that could replace a 5900x or a 10900k. How about one that could replace the CPU in the PS5? Currently one does not exist. You could say one exists for laptops, but that is only available for apple.
    Reply
  • mode_13h - Thursday, May 27, 2021 - link

    > There is currently no high performance ARM processor in existence.

    There are probably a dozen ARM server processors on the market or still in service that would fit a reasonable definition of high-performance.

    > Show me a desktop ARM processor that could replace a 5900x or a 10900k.

    I see you stuck that word "desktop" in there. Desktop is probably the last market ARM would penetrate. So, if your point is that you won't take ARM seriously until there's a competitive ARM-based desktop offering, that's like reaching for the fire extinguisher once you're surrounded by flames instead of when you first smell smoke.

    I'm eager to see what V1-based CPUs look like. Those cores could make for a viable workstation CPU.
    Reply
  • mode_13h - Tuesday, May 25, 2021 - link

    And don't forget about Chinese designs (although this one is mentioned as being A72-derived):

    https://en.wikichip.org/wiki/hisilicon/microarchit...
    Reply
  • SarahKerrigan - Tuesday, May 25, 2021 - link

    The KP920 core isn't A72 derived. It says "from A72" but all it's saying there is that its predecessor used A72's - it's not saying the core is derived from A72's.

    That being said, with Phytium and Hisilicon cut off from TSMC, mainland core development may not result in compelling silicon any time soon.
    Reply
  • eastcoast_pete - Tuesday, May 25, 2021 - link

    Fair point on "no custom cores". However, I don't expect any custom cores from Ampere coming to a smartphone near me anytime soon, and QC seems to want Nuvia's IP mostly for larger systems. Neither strikes me as a source for efficiency cores in the mobile space. QC may incorporate Nuvia's tech into big cores for its SoCs , but I doubt they'd even do that. Reply
  • eastcoast_pete - Tuesday, May 25, 2021 - link

    Addendum: ".. anytime soon" to the end of the last sentence. They probably will try big cores for their SoCs, but I'm afraid they'll pair those with A510 LITTLE cores. Reply
  • mode_13h - Wednesday, May 26, 2021 - link

    > I'm afraid they'll pair those with A510 LITTLE cores.

    As opposed to what? We saw nothing to suggest the A510 is *worse* than A55. And if you're doing ARMv9, then there are no other options (except proprietary).

    Also, why are you freaking out over A510? It's a little underwhelming, but it's not *bad*.
    Reply
  • mode_13h - Wednesday, May 26, 2021 - link

    > QC seems to want Nuvia's IP mostly for larger systems

    No. Nuvia said they were building server cores, but Qualcomm's messaging around the acquisition was that Nuvia will build cores showing up in mobile SoCs, first.

    They didn't rule out the possibility of larger systems, but that's clearly not their priority.
    Reply
  • roboman21 - Tuesday, May 25, 2021 - link

    Apple is lightyears ahead and it is due in no small part to this acquisition:
    https://www.anandtech.com/show/3665/apples-intrins...
    This is tough to pull of but it can yield advantages to a competitor with the same ARM core and 7nM semiconductor process.
    Reply

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