GlobalFoundries Gives 7 nm Capacity Update, Mulls Skipping 5 nmby Anton Shilov on May 31, 2018 12:00 PM EST
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High-ranking executives of GlobalFoundries this month gave several updates concerning future plans of the contract maker of semiconductors. As it appears, in a bid to provide more tangible advantages to its customers and not to invest in short-lasting nodes, the company is mulling skipping 5 nm manufacturing technology like it did with the 10 nm fabrication process. In addition, the company admits that its only leading-edge fab may not have enough capacity for all of its customers at 7 nm, and some of its clients may need to work with other foundries to meet their demand.
7LP On Track for HVM, But Capacities Are Concern
Gary Patton, CTO of GlobalFoundries, said in an interview with EETimes that the company’s first-generation 7LP process technology (7 nm leading performance), which relies exclusively on DUV step and scan systems, is on-track for high-volume manufacturing in the second half of this year. One of the first customers to use this tech will be AMD, which briefly announced its 7LP Vega GPU for a couple of times already. Not everything is rosy with 7LP though.
According to Mr. Patton, since the Fab 8 produces leading edge chips for all of the company’s clients, its 7LP capacity may be limited, which is why AMD may not get enough capacity. The good news is that GF’s 1st Gen 7LP is similar to TSMC’s CLN7FF (which also does not use EUV) and therefore clients with significant demand will be able to port their designs from one foundry to another with some ease. Under the wafer supply agreement signed in 2016, AMD has rights to use foundries other than GlobalFoundries in certain situations. Though whether this capacity-constrained situation actually comes to pass, and whether or not AMD and other partners of GlobalFoundries will have enough time to develop all the designs they need for both foundries should it occur, remains to be seen.
Meanwhile one thing that should be kept in mind is that GlobalFoundries is planning for three generations of 7LP processes, with two of them using EUV lithography and ASML’s Twinscan NXE steppers. As of early 2018, Fab 8 had only one EUV stepper installed with another being constructed. Meanwhile, there is a space for two more, so eventually GlobalFoundries will have four Twinscan NXE machines in Fab 8.
Capacity Expansion May Be Needed for Next Major Node
Earlier this year GlobalFoundries said that to provide its customers a tangible performance, transistor density, and power reduction boost from 7LP, it might need to move to new transistor structure. The company did not disclose any names for its next-gen node and for a reason. Apparently, GlobalFoundries is mulling whether to skip what the industry calls the 5 nm node and jump right to 3 nm. No final decision has been made and there are other concerns.
As leading edge process technologies get more complex and expensive to develop amid rising demand for chips, foundries need to boost their production capacities to remain profitable. Companies like TSMC and Samsung Foundry can land orders from large makers of consumer electronics (Apple, Samsung Electronics, etc.) that can offset development costs of nodes and equipment by ordering huge amounts of chips at premium prices. As a result, to be successful in the long term, GlobalFoundries will not only need to develop competitive process technologies, but also expand its leading edge capacities. Alternatively, GlobalFoundries is open to another process-sharing deal, like the one it signed with Samsung for their 14LPP technology.
Several years ago, GlobalFoundries already considered increasing capacity of the Fab 8 by building an additional module, but the plan was shelved back then. Instead, the company switched some of the equipment in Fab 8 to improve 14LPP supply in 2017. GlobalFoundries is still mulling whether to construct what would be Fab 8 Module 2, but a project like this might require support from the federal government, which is something that the company may not get in the USA. Meanwhile, since GlobalFoundries runs fabs not only in the U.S., but also in Germany and Singapore, another way of adding leading edge capacity would be to upgrade one or two of the non-U.S. facilities assuming that the respective governments provide incentives to the chip maker.
At present it is too early to make any predictions regarding GlobalFoundries’ plans for 5 nm or 3 nm fabrication technologies because they are years away. Meanwhile, if GlobalFoundries is seriously thinking about expanding its leading edge capacities for its next major node, it may have to make its decision rather sooner than later.
- Change of Strategy: A New GlobalFoundries CEO in Dr. Thomas Caulfield
- The Future of Silicon: An Exclusive Interview with Dr. Gary Patton, CTO of GlobalFoundries
- GlobalFoundries Details 7 nm Plans: Three Generations, 700 mm², HVM in 2018
- GlobalFoundries Updates Roadmap: 7 nm in 2H 2018, EUV Sooner Than Later?
- GlobalFoundries to Expand Capacities, Build a Fab in China
- AMD Amends GlobalFoundries Wafer Supply Agreement Through 2020, Gaining New Flexibility & New Costs
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MajGenRelativity - Thursday, May 31, 2018 - linkGlad to see 7nm is on track. I'm interested in seeing what happens afterwards, but for me (consumer and system integrator), all that truly matters is what is shipping right now.
axfelix - Thursday, May 31, 2018 - link3nm sounds extremely made up. I know everyone already talks a lot about how non-Intel fabs tend to inflate (or deflate, I guess) their process size, but 3nm is just a fiction.
deepblue08 - Thursday, May 31, 2018 - linkEverything sounds made-up until it is done. Although, I'm sure 7nm will serve us well for some time.
axfelix - Thursday, May 31, 2018 - linkI'm pretty sure I've read multiple reports (from both Intel and industry groups) that by Intel's numbering, lower than 5nm is physically impossible. It might be that 3nm by non-Intel fabs is roughly equal to Intel's reckoning of 5nm, in which case fair enough, but that is both a stretch and the absolute end of the line.
The Chill Blueberry - Thursday, May 31, 2018 - linkIt's close to impossible on silicon. But if they manage to find a better medium, who knows where it'll stop shrinking..
axfelix - Thursday, May 31, 2018 - linkYeah, I don't want to sound anti-futurist or anything, I think the transistor report I read made clear that it simply wouldn't be viable from a cost perspective to try to shrink any lower for consumer electronics (the implication being that Quantum Computing can do whatever it wants, but we're not going to be recompiling Windows for Quantum platforms) barring some massive breakthrough, given the impracticality.
frenchy_2001 - Thursday, May 31, 2018 - linkPeople were also already saying that for sub-1um.
The crowd chanting "the sky is falling" has been around for a long time.
Technology goes where the money is. If silicon proves a dead end at nanometer scale, someone will find a different solution.
It's not the only side step in history.
Gallium Arsenide is already used for higher frequency (at higher power and leakage) and people are looking into carbon nanotubes.
There may be a pause in progress, but technology marches on...
quorm - Thursday, May 31, 2018 - linkI believe Axfelix is correct. 5/3nm is basically the end of the line, regardless of substrate. My understanding is that at scales below this, quantum effects make behavior unpredictable, outweighing any potential efficiency benefit, assuming you are able to fab something that size with nanotubes or whatever.
Alexvrb - Friday, June 1, 2018 - linkSelf-assembling nano-whatsits.
FullmetalTitan - Saturday, June 2, 2018 - linkThose numbers lost their meaning at about 65nm nodes. 5nm and 3nm will be new transistor designs for most designers. Samsung announced gate all around FETs will be introduced at 5nm for instance. But critical dimensions are still in the 2Xnm range for everyone, naming convention only signifies relative performance improvements meeting the revised moore's law constraint of doubling PERFORMANCE rather than transistor density.
Additionally, anyone with any plan to produce leading edge nodes beyond 2020 is looking into different materials and radical design changes to continue improving efficiency and scale performance.