PCI-SIG this week released version 0.5 of the PCI-Express 7.0 specification to its members. This is the second draft of the spec and the final call for PCI-SIG members to submit their new features to the standard. The latest update on the development of the specification comes a couple months shy of a year after the PCI-SIG published the initial Draft 0.3 specificaiton, with the PCI-SIG using the latest update to reiterate that development of the new standard remains on-track for a final release in 2025.

PCIe 7.0 is is the next generation interconnect technology for computers that is set to increase data transfer speeds to 128 GT/s per pin, doubling the 64 GT/s of PCIe 6.0 and quadrupling the 32 GT/s of PCIe 5.0. This would allow a 16-lane (x16) connection to support 256 GB/sec of bandwidth in each direction simultaneously, excluding encoding overhead. Such speeds will be handy for future datacenters as well as artificial intelligence and high-performance computing applications that will need even faster data transfer rates, including network data transfer rates.

To achieve its impressive data transfer rates, PCIe 7.0 doubles the bus frequency at the physical layer compared to PCIe 5.0 and 6.0. Otherwise, the standard retains pulse amplitude modulation with four level signaling (PAM4), 1b/1b FLIT mode encoding, and the forward error correction (FEC) technologies that are already used for PCIe 6.0. Otherwise, PCI-SIG says that the PCIe 7.0 speicification also focuses on enhanced channel parameters and reach as well as improved power efficiency. 

Overall, the engineers behind the standard have their work cut out for them, given that PCIe 7.0 requires doubling the bus frequency at the physical layer, a major development that PCIe 6.0 sidestepped with PAM4 signaling. Nothing comes for free in regards to improving data signaling, and with PCIe 7.0, the PCI-SIG is arguably back to hard-mode development by needing to improve the physical layer once more – this time to enable it to run at around 30GHz. Though how much of this heavy lifting will be accomplished through smart signaling (and retimers) and how much will be accomplished through sheer materials improvements, such as thicker printed circuit boards (PCBs) and low-loss materials, remains to be seen.

The next major step for PCIe 7.0 is finalization of the version 0.7 of specification, which is considered the Complete Draft, where all aspects must be fully defined, and electrical specifications must be validated through test chips. After this iteration of the specification is released, no new features can be added. PCIe 6.0 eventually went through 4 major drafts – 0.3, 0.5, 0.7, and 0.9 – before finally being finalized, so PCIe 7.0 is likely on the same track.

Once finalized in 2025, it should take a few years for the first PCIe 7.0 hardware to hit the shelves. Although development work on controller IP and initial hardware is already underway, that process extends well beyond the release of the final PCIe specification.

Source: PCI-SIG



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  • ballsystemlord - Thursday, April 4, 2024 - link

    Technical error "This would allow a 16-lane (x16) connection to support 256 GB/sec of bandwidth in each direction simultaneously, excluding encoding overhead."
    It should read 512 GB/sec as shown in the image.
  • rpg1966 - Friday, April 5, 2024 - link

    The second bullet point at top left explains that the bandwidth shown (in your example 512GB/s) is the sum of the receive and transmit bandwidth, giving 256GB/s Tx + 256GB/s Rx = 512GB/s total bandwidth. Reply
  • ballsystemlord - Friday, April 5, 2024 - link

    Thanks! Reply
  • ballsystemlord - Friday, April 5, 2024 - link

    Considering the amount of oscillscopes, spectrum analyzers, and vector network analyzers capable of accurately measuring a 30Ghz signal can be counted on your hands, I'm curious how companies are going to verify and develop PCIe 7.0 chips. I mean, those tools are easily more expensive than a very fancy house here. Reply
  • Threska - Friday, April 5, 2024 - link

    Most likely have a few companies vested in the technology then mass sell to everyone else. Reply
  • Wardrop - Saturday, April 6, 2024 - link

    I remember carefully notching out the back of a 1x or 4x slot with a Dremel to support a pci-e card with a 16x connector. Made me wonder why pci-e doesn't make every slot smaller than 16x open-ended like that. I think that's better than making every slot the same size as a 16x slot as that takes up a lot more room on the motherboard. Reply
  • Eliadbu - Wednesday, April 17, 2024 - link

    imagine long in the future external hardware interface like thunderbolt or USB have 4 lanes of PCI_E 7, you could connect GPUs and SSDs in a singles cable with minor performance loss.
    But getting this speeds working for internal short connection is hard, doing it externally on copper wires with be whole different thing.

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