In the first part of our series on ARM, we mentioned that with every major microprocess design ARM tries to choose 3 licensees to get early access to technology. It's very clear that Samsung was among the early three to get ahold of Cortex A15 IP. Samsung was first on the mobile market with a Cortex A15 based SoC: the Exynos 5250 (aka Exynos 5 Dual). Featuring two cores running at up to 1.7GHz paired with an ARM Mali-T604 GPU, we first met the Exynos 5250 in Samsung's own Chromebook XE303 last October.

The next logical step would be a quad-core version, which we sort of got with the Exynos 5410 - or as it's more commonly known: Exynos 5 Octa. This part features four ARM Cortex A15 cores running at up to 1.6GHz and four ARM Cortex A7 cores running at up to 1.2GHz in a configuration ARM calls big.LITTLE. The specific implementation of big.LITTLE on Exynos 5410 is known as Cluster Migration; either the four Cortex A15 cores or four Cortex A7 cores can be active, but not both and not an arbitrary combination of cores from each island. They're either all on or all off. This is by far the easiest to implement from a software perspective, but is obviously the less interesting option from a heterogeneous SMP perspective. I'll  be talking more about this in an upcoming ARM piece.

On the graphics front, Samsung moved to Imagination Technologies for the Exynos 5410 - implementing a PowerVR SGX 544MP3 setup. The Exynos 5410 saw limited use, appearing in some international versions of the Galaxy S 4 and nothing else. Part of the problem with the design was a broken implementation of the CCI-400 coherent bus interface that connect the two CPU islands to the rest of the SoC. In the case of the 5410, the bus was functional but coherency was broken and manually disabled on the Galaxy S 4. The implications are serious from a power consumption (and performance) standpoint. With all caches being flushed out to main memory upon a switch between CPU islands. Neither ARM nor Samsung LSI will talk about the bug publicly, and Samsung didn't fess up to the problem at first either - leaving end users to discover it on their own. 

Last week Samsung teased a new, improved Exynos 5 Octa - the Exynos 5420. Today we got the first details of the new SoC. The base CPU architecture remains unchanged. Samsung outfitted the Exynos 5420 with four A15s and four A7s, presumably in the same Cluster Migration big.LITTLE configuration. Clock speeds on both clusters are a bit higher now, 1.8GHz is the top speed for the Cortex A15 cores while 1.3GHz is where the A7s top out. Note that on the Cortex A15 side this exceeds where even ARM recommends clocking Cortex A15 for smartphones as far as power efficiency is concerned, but it should be fine for tablets. There's no word on whether or not the CCI-400 bug has been fixed, but I can only assume that it has been otherwise it'd be senseless to do another Exynos 5 Octa release this close to the original. Update: It looks like the CCI bug has been fixed.

Exynos 5 Comparison
SoC 5250 5410 5420
Max Number of Active Cores 2 4 4 (?)
CPU Configuration 2 x Cortex A15 4 x Cortex A15 + 4 x Cortex A7 4 x Cortex A15 + 4 x Cortex A7
A15 Max Clock 1.7 GHz 1.6GHz 1.8GHz
A7 Max Clock - 1.2GHz 1.3GHz
GPU ARM Mali-T604 MP4 Imagination PowerVR SGX544MP3 ARM Mali-T628 MP6
Memory Interface 2 x 32-bit LPDDR3-1600 2 x 32-bit LPDDR3-1600 2 x 32-bit LPDDR3-1866
Process 32nm HK+MG 28nm HK+MG 28nm HK+MG(?)

For the GPU Samsung switches back to ARM, this time using the Mali-T628 GPU in a 6-core configuration. Mali-T628 is actually a second generation implementation of ARM's Midgard GPU architecture first demonstrated with the T604. The second generation brings higher IPC and higher clocks in the same physical area as the first-gen cores, the combination of the two results in up to a 50% increase in performance. The T604 was a four-core implementation, so we should see another 50% on top of that with the move to 6-cores in the 5420. A six-core configuration is a bit odd in that we've never seen one before, but the T628 is scalable from 4 - 8 cores so it's a valid config.

On the memory interface front the Exynos 5420 retains a dual-channel LPDDR3 interface (2 x 32-bit) with support for up to 1866MHz memory, resulting in peak theoretical memory bandwidth of 14.9GBps. 

The biggest question about the new Exynos 5420 is whether or not the cache coherency issues have been worked out. The solution remains a bit on the large side for most price sensitive tablets, but it could make for an interesting use case in a higher-end tablet. In smartphones I'm still not sold on the idea of having four Cortex A15s running at up to 1.8GHz. Although big.LITTLE is one answer to the problem of getting the best of both worlds (low power and high performance), Qualcomm seems to have a pretty good solution with its Krait 300/400 cores. If Samsung were to enable one of the more interesting big.LITTLE scheduling models in its products however (e.g. big.LITTLE MP, all cores visible at once, intelligent scheduling based on perf needs) I'd be more interested.

Source: Samsung

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  • lmcd - Tuesday, July 23, 2013 - link

    A bit weaker than Adreno 320, and iPhone 5 does well against Adreno 320 in most tests I believe.
  • Łukasz Markiewicz - Tuesday, July 23, 2013 - link

    Does anyone have a link to a write up on the cache coherency issue? Can't find anything on Anand under the "exynos 5 octa" tag, but I'm sure this has been mentioned before. I vaguely remember hearing about it on one of the podcasts. Maybe around the time of the S4 review, though Anandtech's reviews was of the S600 version. Hmm...
  • mrtanner70 - Tuesday, July 23, 2013 - link

    I think the bug might actually have been more of a deliberate cripple to match the s600. It would have been a marketing disaster in LTE markets for Samsung to have the international version of the s4 show any serious advantage. They had the CCI working fine for demos months earlier and it's a big issue to get through if not by design....if it was deliberate they would certainly not talk about it.
  • mrtanner70 - Tuesday, July 23, 2013 - link

    And for Anand, 8 cores may well be visible.
  • rd_nest - Tuesday, July 23, 2013 - link

    Some info here:

    Andrei always has good knowledge on Exynos SOCs. He even mentioned the 5420 info before it was officially announced.
  • yowanvista - Tuesday, July 23, 2013 - link

    It appears that the 5420 can effectively use any combination of the eight CPU cores at a time if Global Task Scheduling is used instead of In-Kernel Switcher. Of course that's up to Samsung.
  • rd_nest - Tuesday, July 23, 2013 - link

    AndreiLux says GTS is working.
  • FowLang - Tuesday, July 23, 2013 - link

    The HMP (Linaro) would be dependent on which kernel they would be running if im not mistaken. I think that it was implemented in 3.9, so until Android (the assumption here is that these SoC will be used in the Note and an updated S4) upgrades from 3.4 or whatever it is at now, this wont be possible, unless Samsung can port/patch the implementation in their build of the OS. Hopefully the CCI-400 issue is resolved.
  • Krysto - Tuesday, July 23, 2013 - link

    Btw, now I think I know why Samsung went with PowerVR. I don't think they had a Mali alternative for the late spring 2013 launch. There was Mali T604 in fall 2012, and Mali T628 in fall 2013, and I don't think Mali T624 was ready either.

    So that's why they probably went with PowerVR "all of the sudden" (it surprised everyone), and probably why the cache coherency didn't work too well, either, because I think ARM mainly optimized it for its Mali chips, and Imagination, if anything, will optimize for that in PowerVR Series6, and didn't revist the old PowerVR 5 to make it work well with ARM's cache interconnect.
  • aegisofrime - Tuesday, July 23, 2013 - link

    I'm a prospective Note 3 buyer... So this concerns me personally I guess.

    So, the problem with big.LITTLE from an Android perspective is not just that the Linux scheduler can't take full advantage of it, but also there's a hardware bug causing performance and power efficiency to suffer?

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