"Roman states that only two of the dies are enabled"
Which was just a rather uneducated guess, since he destroyed the chip, thus his plans to measure which dies are operational failed.
There is only one good reason for TR to have 4 dies, and that has nothing to do with "rigidity" - 2 dies rotated at 90 degrees would have been pretty stable.
The most likely reason is that AMD is salvaging cores here. There are 3 things that can fail and still get a salvaged chip - CPU cores, PCIE lanes and MC channels.
Ryzen doesn't have full PCIE, so I assume chips with defects in PCI lanes went into that line.
Flawless chips were obviously reserved for top of the line Epyc, which comes with full PCIE count and full MC count.
So what does AMD do with a chip that has a failed memory controller channel? Throw it away? Well, AMD's zen design has the prospect to allow to salvage those chips.
By using all four dies in TR, then each die has a single channel memory controller, and only 4 active cores. So the reduced bandwidth won't be that much of an issue as the number of cores is also halved, and 4 dies make up for a total of 4 memory channels for the CPU.
Of course this is just speculation, but at least it makes sense logically and more importantly - economically. I totally do expect to see a 2 die TR design further down the line, especially if sales are good, which they should, considering the very competitive pricing. Naturally, they might as well have "emulated" a TR out of an Epyc chip just for the sake of having a demo product, but the prospect of salvaging dies with defective MC channels is not to be dismissed, the MC takes a significant die area so a considerable number of defects will inevitably happen to be in that area.
The good news is that since it is basically the same socket as Epyc, AMD is cutting R&D cost and also allowing the possibility for more than 16 core threadrippers in the future.
I saw the video before it was taken down and I'm pretty confident Roman specifically said he asked AMD about the die arrangement and they confirmed that only two dies were enabled. The way he worded it (assuming I'm remembering correctly, which I believe I am), it was info direct from AMD.
Are AMD failure rates on memory controllers really high enough to make it cost effective to populate their entire HEDT product line with double the Zen dies anyway? That seems unlikely to me.
TR will in all likelihood be selling in the lowest quantities of all zen products. A rather crude estimate would put defects in the MC at about 15%.
Amd did claim pretty good yield, but I assume that's simply parts that are useless, while parts that can be salvaged go into the "good yield" category, either entirely or at the very least as much as the percent of the chip that can be salvaged.
At any rate, AMD is so poor it will most likely be interested in salvaging as much as possible rather than putting twice the needed dies and disabling half of that, or even pay to integrate useless silicon into chip packages.
i figured the dies would be much closer together than what is pictured. That's a awful lot of wasted space. it appears the top left and bottom right are the fake cores judging by the supporting electronics surrounding each "package".
There are four dies but only one package. You make it sound trivial to make a package like this. The epyc/threadripper package is the most amazing thing I've ever seen accomplished in consumer electronics. I'm not a fanboy of any company but this is what real innovation looks like. They made the effort to prove that just because it sounds hard doesn't mean it's impossible. You're saying the dies are too far apart for your liking? I promise you that their exact locations are the furthest thing from an accident.
Correct me if I did something wrong but the trace length adds less than one cycle of latency. What's more is that sharing between caches is something that is very architecture specific and if the interconnect had limitations there are decisions they can make to rely on the interconnect less (there is a lot of literature on this and the comments section of an article isn't the right place to discuss it). https://en.wikipedia.org/wiki/Cache_(computing) https://en.wikipedia.org/wiki/Cache_coherence
Oh I forgot: in the cases where the traces have to go diagonally there will likely be 1-2 cycles of latency added from the trace length. However data would only need to go through this when there is an L3 miss. L3 access time (at least when I was checking on intel parts a few years ago) is already in the dozens of cycles so the trace length does not add a significant amount of time.
8-core TR with 60 PCIe lanes for HBAs would be a decent storage box for ZFS, btrfs, etc. That's a lot of x8 controllers connected to hard drives. Could be a decent upgrade to our Opterons 61xx, 62xx, and 63xx based storage systems.
You have 8C Epyc for that if its CPU is good enough. Costs even less for twice the lanes. If not, 24C 1P costs double and offers you double PCIe lanes. And likely with better board selection for that purpose - TR boards might lack 2x 10Gbit Ethernet.
EPYC won't be supported in the TR4 socket. Pin-outs are different, especially with eight-channel memory and the PCIe lanes. CPUs will be notched differently as well.
"Pin-outs are different, especially with eight-channel memory and the PCIe lanes"
Care to provide a source for that claim? To me it looks like TR4 and SP3 are identical, and AMD did it to save on having to develop another whole socket for TR which should be a fairly niche product.
If intel shoehorned desktop chips in a hedt socket, despite it has half of everything and doesn't utilize more than half of the pins, it doesn't seem far fetched for AMD to do something similar.
I don't say that you'd be able to put TR in an Epyc socket or vice versa and get it to work. I just say the two sockets are actually the same physical socket, the same number of pins, and I highly doubt AMD has the motivation to waste resources or making pinouts different, when there is no need to and it will actually require a lot of extra work for no actual benefit.
"One of AMD’s skills in recent quarters is the ability to drip feed information about upcoming products slowly to the point where even the breath of a clock speed becomes another several column inches about an upcoming platform."
I feel played, but its been fun - like a treasure hunt.
AMD are sure executing their marketing well, and as you say, getting advertising you cant buy, for a song.
I've read suggestions that the EPYC and Threadripper use the same heat spreader, which would explain why AMD needs spacers. In an engineering sample, it's possible that they actually used defective dies as spacers--they would be precisely the right thickness and early runs might have produced a good supply of useless chips. For volume manufacturing, aluminum spacers might make sense, but given the size of the spacers they could afford to use bulk silicon.
As for the TR 1900X, it may not end up being a big seller, but I think it at least makes more sense that Intel's i7-7740X. The 7740X plugs into a HEDT board, but you lose the majority of the PCIe lanes and two of the memory channels. In contrast, with 1900X the motherboard is fully functional.
I think that if it comes with 4 dies in the retail version, which we don't know for sure yet but seems credible as they could use the exact same tooling as for Epyc saving a lot of process complexity and machinery, then the "disabled" dies would be bulk silicon. You do not want to mix and match materials with vastly different thermal characteristics inside a CPU package. That would be a recipe for disaster.
The 1900X makes sense if you view it from the perspective that Threadripper isn't "just" supposed to be a high end desktop but can also replace Xeon workstations in most cases, and here a lower core count variant makes perfect sense due to a good deal of workstation workloads really don't need that many cores but do need a lot of PCIe lanes for GPU acceleration, and lots of ECC RAM.
More puzzling is why they even went with the same size as Epyc. Purely for saving costs on packaging? TR could be a much smaller package and socket which would lead to cheaper mobos and in general lower platform costs.
AMD is using basically the same silicon across all their hardware except the upcoming Raven Ridge. It's a case of cost and support - the more different platforms there are, the more people AMD needs internally to support the infrastructure for that platform. The chipsets are designed by ASMedia at this point, until they have enough backing them to design their own chipsets again.
this is the reason I believe all four dies are actually active: bigger savings from having only 2 sockets/packages to design: 1 die for consumer, 4 dies for server. TR will be the salvage option for failed server parts.
looking at the traces from T1beriu, it would be a big effort to build new tracing to only have spacers. having all dies active (even if 2 of them are only using the interconnect fabric), seems a lot easier than re-tracing the package.
They won't sell all that many TRs. A whole another socket for a niche product will end up costing them far more money and efforts to design and support than the overkill in putting TR in Epyc packaging.
It makes since just like the Ryzen line with the quad cores essentially being the same silicon as the 8-cores. The upside that I don't think has been mentioned is that AMD has a pretty easy path to up core counts on Threadripper if they want.
What leaks? Those slides are publicly available, and all other sites have them without any watermarks. Which begs the question why do it in the first place.
Nope. Watermarks are AMD's doing, so if the slides leaked early they can trace to the source. It's amazing what people will say when they don't have facts but think they're right.
Listed mobos for now at 350$ and up, this platform is DOA ,they need cheaper SKUs and cheaper mobos. Otherwise the not clueless folk will just get Naples.
Isn't that actually pretty decent for workstation motherboards? They usually go upwards of $500. I guess it depends on the details and what you get onboard, but I wouldn't compare the prices to standard desktops. The Intel x299 Aorus 7 is $399.
Also keep in mind the Epyc (and comparable xeons for that matter) are in the 2.1-3.0Ghz range. So you may get even more IO at about the same price for CPU and maybe a $500 server motherboard, you lose a lot of single threaded performance. Threadripper seems to be less compromise on that front.
If you think Threadripper and its platform are expensive then HEDT is not for you. This isn't for your gaming machine, granted yes you can game on it, its for workstations doing real work using 32 threads. This will be the cheapest 32 thread CPU to land on a consumer i.e. no server platform ever.
The 1900X is going to be a great CPU. I was hoping they'd do this, as I don't necessarily need 12 cores but I want the PCIe lanes. Not too expensive, extra MHz, thermal headroom for overclocking, all of the IO bells and whistles.
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bubblyboo - Sunday, July 30, 2017 - link
Epycddriver - Monday, July 31, 2017 - link
"Roman states that only two of the dies are enabled"Which was just a rather uneducated guess, since he destroyed the chip, thus his plans to measure which dies are operational failed.
There is only one good reason for TR to have 4 dies, and that has nothing to do with "rigidity" - 2 dies rotated at 90 degrees would have been pretty stable.
The most likely reason is that AMD is salvaging cores here. There are 3 things that can fail and still get a salvaged chip - CPU cores, PCIE lanes and MC channels.
Ryzen doesn't have full PCIE, so I assume chips with defects in PCI lanes went into that line.
Flawless chips were obviously reserved for top of the line Epyc, which comes with full PCIE count and full MC count.
So what does AMD do with a chip that has a failed memory controller channel? Throw it away? Well, AMD's zen design has the prospect to allow to salvage those chips.
By using all four dies in TR, then each die has a single channel memory controller, and only 4 active cores. So the reduced bandwidth won't be that much of an issue as the number of cores is also halved, and 4 dies make up for a total of 4 memory channels for the CPU.
Of course this is just speculation, but at least it makes sense logically and more importantly - economically. I totally do expect to see a 2 die TR design further down the line, especially if sales are good, which they should, considering the very competitive pricing. Naturally, they might as well have "emulated" a TR out of an Epyc chip just for the sake of having a demo product, but the prospect of salvaging dies with defective MC channels is not to be dismissed, the MC takes a significant die area so a considerable number of defects will inevitably happen to be in that area.
The good news is that since it is basically the same socket as Epyc, AMD is cutting R&D cost and also allowing the possibility for more than 16 core threadrippers in the future.
rhysiam - Monday, July 31, 2017 - link
I saw the video before it was taken down and I'm pretty confident Roman specifically said he asked AMD about the die arrangement and they confirmed that only two dies were enabled. The way he worded it (assuming I'm remembering correctly, which I believe I am), it was info direct from AMD.Are AMD failure rates on memory controllers really high enough to make it cost effective to populate their entire HEDT product line with double the Zen dies anyway? That seems unlikely to me.
ddriver - Monday, July 31, 2017 - link
TR will in all likelihood be selling in the lowest quantities of all zen products. A rather crude estimate would put defects in the MC at about 15%.Amd did claim pretty good yield, but I assume that's simply parts that are useless, while parts that can be salvaged go into the "good yield" category, either entirely or at the very least as much as the percent of the chip that can be salvaged.
At any rate, AMD is so poor it will most likely be interested in salvaging as much as possible rather than putting twice the needed dies and disabling half of that, or even pay to integrate useless silicon into chip packages.
ZippZ - Monday, July 31, 2017 - link
Could also be blocks of plain unprocessed silicon too.ddriver - Monday, July 31, 2017 - link
Judging by the distribution of those tiny components on the end of the chip, it doesn't look that there is any "dummy" or disabled dies.Sure, two of the dies have only half of the components, but they still have the other half.
Morawka - Sunday, July 30, 2017 - link
i figured the dies would be much closer together than what is pictured. That's a awful lot of wasted space. it appears the top left and bottom right are the fake cores judging by the supporting electronics surrounding each "package".boozed - Sunday, July 30, 2017 - link
The size of these modules, even with a single die, has always been dictated by the size and number of pins/pads on the module.yankeeDDL - Monday, July 31, 2017 - link
Have you looked at the pinout of Threadripper? How do you make it any smaller?T1beriu - Monday, July 31, 2017 - link
1. You can't cut the pins.2. Traces need room. It's not wasted space: https://i.redditmedia.com/s7rVI_fRxqhQ_etQfjoq2fxV...
willis936 - Monday, July 31, 2017 - link
There are four dies but only one package. You make it sound trivial to make a package like this. The epyc/threadripper package is the most amazing thing I've ever seen accomplished in consumer electronics. I'm not a fanboy of any company but this is what real innovation looks like. They made the effort to prove that just because it sounds hard doesn't mean it's impossible. You're saying the dies are too far apart for your liking? I promise you that their exact locations are the furthest thing from an accident.Morawka - Monday, July 31, 2017 - link
not to my liking, but to the CPU's cache latency liking.willis936 - Monday, July 31, 2017 - link
https://www.wolframalpha.com/input/?i=(22.01+*+0.7...Approximated the distance as 70% of the die width. Die width taken from here:
https://en.wikichip.org/wiki/amd/ryzen_7/1800x#Die...
Correct me if I did something wrong but the trace length adds less than one cycle of latency. What's more is that sharing between caches is something that is very architecture specific and if the interconnect had limitations there are decisions they can make to rely on the interconnect less (there is a lot of literature on this and the comments section of an article isn't the right place to discuss it).
https://en.wikipedia.org/wiki/Cache_(computing)
https://en.wikipedia.org/wiki/Cache_coherence
willis936 - Monday, July 31, 2017 - link
Oh I forgot: in the cases where the traces have to go diagonally there will likely be 1-2 cycles of latency added from the trace length. However data would only need to go through this when there is an L3 miss. L3 access time (at least when I was checking on intel parts a few years ago) is already in the dozens of cycles so the trace length does not add a significant amount of time.ddriver - Tuesday, August 1, 2017 - link
Yeah, but 2 cycles is too much for intel fanboys, who do not stoop to such a low level of using inferior "glued together" chips.phoenix_rizzen - Sunday, July 30, 2017 - link
8-core TR with 60 PCIe lanes for HBAs would be a decent storage box for ZFS, btrfs, etc. That's a lot of x8 controllers connected to hard drives. Could be a decent upgrade to our Opterons 61xx, 62xx, and 63xx based storage systems.msroadkill612 - Monday, July 31, 2017 - link
I hear you can have an epyc 1P 24core w/ 128 lanes for about $70usd more.phoenix_rizzen - Thursday, August 3, 2017 - link
That's a little overkill (on CPU cores) for a straight storage server, though.Zizy - Monday, July 31, 2017 - link
You have 8C Epyc for that if its CPU is good enough. Costs even less for twice the lanes. If not, 24C 1P costs double and offers you double PCIe lanes. And likely with better board selection for that purpose - TR boards might lack 2x 10Gbit Ethernet.Ian Cutress - Monday, July 31, 2017 - link
EPYC won't be supported in the TR4 socket. Pin-outs are different, especially with eight-channel memory and the PCIe lanes. CPUs will be notched differently as well.ddriver - Monday, July 31, 2017 - link
"Pin-outs are different, especially with eight-channel memory and the PCIe lanes"Care to provide a source for that claim? To me it looks like TR4 and SP3 are identical, and AMD did it to save on having to develop another whole socket for TR which should be a fairly niche product.
If intel shoehorned desktop chips in a hedt socket, despite it has half of everything and doesn't utilize more than half of the pins, it doesn't seem far fetched for AMD to do something similar.
I don't say that you'd be able to put TR in an Epyc socket or vice versa and get it to work. I just say the two sockets are actually the same physical socket, the same number of pins, and I highly doubt AMD has the motivation to waste resources or making pinouts different, when there is no need to and it will actually require a lot of extra work for no actual benefit.
Ian Cutress - Monday, July 31, 2017 - link
Yes, it's the same physical socket, like 775 and 771 were. But we're told the pin-outs are different.msroadkill612 - Tuesday, August 1, 2017 - link
Its official - DONT put a TR in an epyc mobo socket. It wont work and may fry.msroadkill612 - Sunday, July 30, 2017 - link
Delightfully put:"One of AMD’s skills in recent quarters is the ability to drip feed information about upcoming products slowly to the point where even the breath of a clock speed becomes another several column inches about an upcoming platform."
I feel played, but its been fun - like a treasure hunt.
AMD are sure executing their marketing well, and as you say, getting advertising you cant buy, for a song.
msroadkill612 - Sunday, July 30, 2017 - link
re:"the main four companies ....
ASRock, ASUS, GIGABYTE and MSI will all be launching motherboards on day one,...
We’re planning a full overview of each board,"
It would be a valuable service. Look forward to it.
KAlmquist - Monday, July 31, 2017 - link
I've read suggestions that the EPYC and Threadripper use the same heat spreader, which would explain why AMD needs spacers. In an engineering sample, it's possible that they actually used defective dies as spacers--they would be precisely the right thickness and early runs might have produced a good supply of useless chips. For volume manufacturing, aluminum spacers might make sense, but given the size of the spacers they could afford to use bulk silicon.As for the TR 1900X, it may not end up being a big seller, but I think it at least makes more sense that Intel's i7-7740X. The 7740X plugs into a HEDT board, but you lose the majority of the PCIe lanes and two of the memory channels. In contrast, with 1900X the motherboard is fully functional.
SaturnusDK - Monday, July 31, 2017 - link
I think that if it comes with 4 dies in the retail version, which we don't know for sure yet but seems credible as they could use the exact same tooling as for Epyc saving a lot of process complexity and machinery, then the "disabled" dies would be bulk silicon. You do not want to mix and match materials with vastly different thermal characteristics inside a CPU package. That would be a recipe for disaster.The 1900X makes sense if you view it from the perspective that Threadripper isn't "just" supposed to be a high end desktop but can also replace Xeon workstations in most cases, and here a lower core count variant makes perfect sense due to a good deal of workstation workloads really don't need that many cores but do need a lot of PCIe lanes for GPU acceleration, and lots of ECC RAM.
KAlmquist - Tuesday, August 1, 2017 - link
Good point about the thermal characteristics.serendip - Monday, July 31, 2017 - link
How about adding some Epyc SKUs to the table? I'd like to see how TR pricing compares, especially when Epyc has a lot more PCIE lanes.beginner99 - Monday, July 31, 2017 - link
More puzzling is why they even went with the same size as Epyc. Purely for saving costs on packaging? TR could be a much smaller package and socket which would lead to cheaper mobos and in general lower platform costs.Ian Cutress - Monday, July 31, 2017 - link
AMD is using basically the same silicon across all their hardware except the upcoming Raven Ridge. It's a case of cost and support - the more different platforms there are, the more people AMD needs internally to support the infrastructure for that platform. The chipsets are designed by ASMedia at this point, until they have enough backing them to design their own chipsets again.marc1000 - Monday, July 31, 2017 - link
this is the reason I believe all four dies are actually active: bigger savings from having only 2 sockets/packages to design: 1 die for consumer, 4 dies for server. TR will be the salvage option for failed server parts.looking at the traces from T1beriu, it would be a big effort to build new tracing to only have spacers. having all dies active (even if 2 of them are only using the interconnect fabric), seems a lot easier than re-tracing the package.
https://i.redditmedia.com/s7rVI_fRxqhQ_etQfjoq2fxV...
ddriver - Monday, July 31, 2017 - link
They won't sell all that many TRs. A whole another socket for a niche product will end up costing them far more money and efforts to design and support than the overkill in putting TR in Epyc packaging.FreckledTrout - Monday, July 31, 2017 - link
It makes since just like the Ryzen line with the quad cores essentially being the same silicon as the 8-cores. The upside that I don't think has been mentioned is that AMD has a pretty easy path to up core counts on Threadripper if they want.ddriver - Monday, July 31, 2017 - link
It has been mentioned in the article and the comments as well :)regis440 - Monday, July 31, 2017 - link
Linus yesterday made unboxing of A-51 with run of CB15 with 2,866 score :) https://www.youtube.com/watch?v=twkZz5WyVJsT1beriu - Monday, July 31, 2017 - link
Wow! These watermarks! AMD really wants to put a stop to leaks.ddriver - Monday, July 31, 2017 - link
What leaks? Those slides are publicly available, and all other sites have them without any watermarks. Which begs the question why do it in the first place.petteyg359 - Monday, July 31, 2017 - link
Those ridiculous watermarks are anandtech's stupidity, not AMD's. Read the email address carefully.Ian Cutress - Monday, July 31, 2017 - link
Nope. Watermarks are AMD's doing, so if the slides leaked early they can trace to the source. It's amazing what people will say when they don't have facts but think they're right.ddriver - Tuesday, August 1, 2017 - link
So, AMD is only giving YOU watermarked images, while the rest of the sites get non-watermarked?Geez, maybe it is high time you remove that "The Most Trusted in Tech Since 1997" ;)
jjj - Monday, July 31, 2017 - link
Listed mobos for now at 350$ and up, this platform is DOA ,they need cheaper SKUs and cheaper mobos.Otherwise the not clueless folk will just get Naples.
sor - Monday, July 31, 2017 - link
Isn't that actually pretty decent for workstation motherboards? They usually go upwards of $500. I guess it depends on the details and what you get onboard, but I wouldn't compare the prices to standard desktops. The Intel x299 Aorus 7 is $399.sor - Monday, July 31, 2017 - link
Also keep in mind the Epyc (and comparable xeons for that matter) are in the 2.1-3.0Ghz range. So you may get even more IO at about the same price for CPU and maybe a $500 server motherboard, you lose a lot of single threaded performance. Threadripper seems to be less compromise on that front.Alexvrb - Monday, July 31, 2017 - link
There you go dropping facts and such. How dare you, sir!FreckledTrout - Tuesday, August 1, 2017 - link
If you think Threadripper and its platform are expensive then HEDT is not for you. This isn't for your gaming machine, granted yes you can game on it, its for workstations doing real work using 32 threads. This will be the cheapest 32 thread CPU to land on a consumer i.e. no server platform ever.Kvaern1 - Monday, July 31, 2017 - link
$549 for the 1900X is a pleasent surprise.$549 for the 1900 and and $599 for 1900X seemed to be the logical price points.
sor - Monday, July 31, 2017 - link
The 1900X is going to be a great CPU. I was hoping they'd do this, as I don't necessarily need 12 cores but I want the PCIe lanes. Not too expensive, extra MHz, thermal headroom for overclocking, all of the IO bells and whistles.Glock24 - Monday, July 31, 2017 - link
What! No Mini-STX boards for launch? LolAlexvrb - Monday, July 31, 2017 - link
I'm holding out for the 35W models. :Pmsroadkill612 - Tuesday, August 1, 2017 - link
Our is not to ryzen why,Ours is just to duo die.
Lolimaster - Tuesday, August 1, 2017 - link
The avrg cinebench score for 1950X is 2900, not 27**. With faster memory is around 3000.