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  • Arnulf - Thursday, September 6, 2018 - link

    Another interesting read from Anton! You and Andrei are really an asset to AT.

    Thank you for bringing forth more technical info rather than just the everyday fanboy squabble material :)
  • Holliday75 - Thursday, September 6, 2018 - link

    This is why I love these guys. I don't understand half the jargon and acronyms, but over the years I have learned quite a bit reading these articles. I can give out basic details on manufacturing process that nobody else knows or wants to hear. :)
  • jospoortvliet - Saturday, September 8, 2018 - link

    Same here - this is my favourite content combined with the architecture deep dives and investigative stuff Andrei does.
  • eastcoast_pete - Thursday, September 6, 2018 - link

    Thanks Anton! Question: Did Samsung make any statements on how many wafers (and of which size) their "8 nm" LPU is capable of producing in 2018 and then 2019, and how many 7 nm LPP wafers they project to produce in 2019? I put the "8 nm" in quotation marks, as it reminds me a bit of Intel's "14nm+" and "++"; nevertheless, Samsung making their 10 nm process more compact and supposedly more efficient is a smart move, and should help them gear up mass production.
  • melgross - Thursday, September 6, 2018 - link

    Of the big three, Samsung is the least efficient.
  • iwod - Thursday, September 6, 2018 - link

    Basically the initial 7nm capacity will only be used for Samsung Galaxy 10 coming in next Feb or March. You are talking about ~10M unit per quarter. The other half will be using Qualcomm Snapdragon 855 and we don't know if it is Samsung or TSMC 7nm yet.

    On the other hand, TSMC are making roughly ~70M 7nm SoC for Apple and Huawei per first quarter.

    On another notes, lots of people likes to argue about how good Samsung is and how Samsung was suppose to be HVM 7nm in 2018 ( which is proved to be incorrect again ) you can deduce the number of EUV machines from ASML report and have educated guess. Assuming the rumoured of Qualcomm going back to TSMC 7nm being true, which means Samsung with two months lead time only manage to produce enough 7nm SoC for its Samsung Flashship. Or basically 10M unit per quarter.

    ( Before someone correct me, Samsung sell less Exynos SoC than Qualcomm SoC version of Galaxy, the 10M was only a simple half separation between the est 20M per quarter sales target )
  • V900 - Thursday, September 6, 2018 - link

    Qualcomm is already a customer with TSMC, they take up around 5% of their 7nm output, according to industry sources.

    As for Samsung’s 7nm production, we don’t know how many 7nm Exynos chips they have sold/will sell to other OEMs.

    Samsung’s Foundry is independent of Samsung’s Consumer Electronics arm, and if they can sell the Exynos SOCs to other manufacturers, they absolutely will. (As they have done before, with mixed results)
  • FreckledTrout - Thursday, September 6, 2018 - link

    So do you think they will have 4nm in high volume by 2020? That surly would make some interesting APU's.

    The 3d packaging is just neet.
  • V900 - Thursday, September 6, 2018 - link

    Don’t count on it.

    Every node lately have seen significant delays across all foundries.

    There’s no reason to expect that not to continue.

    Heck, the chances of not just Samsung’s, but anyone’s 3-4nm node never seeing the light of day are probably 50-50 at this point.

    Regardless of optimistic 2020-schedules for the analysts.
  • Death666Angel - Friday, September 7, 2018 - link

    "Every node lately have seen significant delays across all foundries."
    TSMC said in a 2016 report that it expected volume 7nm production in early 2018 and in April 2018 they announced HVM of first gen 7nm based chips. Are you from Intel trying to make everyone look equally bad, thus making Intel look less bad by comparison?
  • haxxiy - Friday, September 7, 2018 - link

    Their nodes aren't as complex as Intel's though, despite their fancy naming. All of those "7 nm" nodes indeed, and Intel's own 10 nm node, would have been called 11 nm if we had followed the ITRS' guidelines and not names for marketing. I assume their "5 nm" is actually a node upgrade like "8 nm", not even a half-node, and their "3 nm" is what would have been called a 8 nm by ITRS - that is, the full node below 11 nm.
  • melgross - Thursday, September 6, 2018 - link

    Interesting that Samsung is going to use finFET for 5nm, since it’s been understood that it doesn’t work well below 7nm, and that alternatives need to be used. Alternatives that haven’t yet been wrung out.

    I’m still skeptical About 5nm from anyone, and much more so about 3nm. The only thing I can see happening is that these technology levels will be even less of what they claim than 14 and 10nm, from most fabs.
  • haukionkannel - Thursday, September 6, 2018 - link

    Those marketing nm has nothing to do with real physics... They only tell that 3nm in newer edition of 5nm that is a newer edition of 10nm and so on without any real Connection to the real size of the technology... Soon They claim smaller than Atom size because They will run out number that Are bigger than a Atom ;) that will be hilarious!
  • V900 - Thursday, September 6, 2018 - link

    Consider the usual jump in nodes we see from everyone but Intel.*

    Samsung’s/TSMCs “5nm” node would be a 7-8nm node at Intel.

    *Obviously that doesn’t mean that Intel is a 100% straight shooter either, when it comes to node-size. The smallest part of their 10nm node is around 38nm, as I recall.

    With that in mind, FINFETs fit.
  • Santoval - Friday, September 7, 2018 - link

    "The smallest part of their 10nm node is around 38nm, as I recall."
    It depends on how you define the "smallest part". For instance the fin width of Intel's 10nm node is 7nm. Should that count as the transistor's smallest feature or not? If not why?
    By the way, the fin width of Intel's 14nm is 8nm. Wikichip has no data for Intel's 10nm node gate length, but their 14nm node's one is 20nm, and their 22nm node's one is 26nm, so the gate length of their 10nm node should be around 14nm.
  • edzieba - Thursday, September 6, 2018 - link

    I guess 7PLE was quietly taken out behind the woodshed.
  • Cellar Door - Thursday, September 6, 2018 - link

    This is very interesting - who knows GloFlo might end up licensing another process from Samsung.
  • haukionkannel - Thursday, September 6, 2018 - link

    Hopefully because having only two manufacturers making chips is not good to customers in long run...
  • V900 - Thursday, September 6, 2018 - link

    Highly doubtful if there’s room for more than two sub 10nm foundries. (plus Intel)

    There certainly isn’t room for more than two profitable ones.

    The market is too small and the investments too big for more than that.

    There are already reports that no Android manufacturers will launch phones with 7nm SOCs in 2019. They’re too expensive for anyone but Apple.
  • porcupineLTD - Friday, September 7, 2018 - link

    you mean 2018
  • V900 - Thursday, September 6, 2018 - link

    Whoops, forgot to post these links in my reply.

    https://pocketnow.com/7nm-technology-transition

    https://appleinsider.com/articles/18/09/04/develop...
  • V900 - Thursday, September 6, 2018 - link

    Nah... By the time Samsung get their process up and running, they won’t be able to for financial reasons:

    *Samsung will have invested billions into their 7nm node(s).

    *The market for 7nm is pretty small compared to the overall market. It’s too expensive, only a limited amount of customers need (or can afford to pay for) that kind of performance.

    *Samsung will want to recoup their investment. That’s less likely to happen if they license it out.
  • Death666Angel - Friday, September 7, 2018 - link

    Depends on the licensing terms and that's up to the negotiating parties. If the therms are beneficial to both parties, why not? After licensing it in a few years, it will also take a while to order the necessary machines and ready a fab, so it's not like they will be immediate rivals. As I understand the GloFo situation, they are doing nothing 7nm related anymore, so it would make sense to license it, once Samsung has recouped most of the initial investment or is on a newer node already. Pretty sure every node advance in the last decade or more has cost billions to research, so that's no reason why they won't license it out.
  • Morawka - Thursday, September 6, 2018 - link

    Intel's lithography advantage appears to be on its deathbed. They wasted too much time on 10nm.
  • iwod - Thursday, September 6, 2018 - link

    TSMC Roadmap

    2018 - 7nm
    2019 - 7nm+
    2020 - 5nm ( Half EUV )
    2021 - 3nm ( Full / Most EUV )
    2022 - likely be a refined 3nm+

    You can literally bet all these will be shipped to a big customer in Dozen millions of unit at September every year. So there are no Risk Production or HVM word play, they are the deadline which is done and shipped as final product.
  • porcupineLTD - Friday, September 7, 2018 - link

    Yeah, because samsung invented those terms.
  • Santoval - Friday, September 7, 2018 - link

    I wonder how Samsung will manage the "trapped heat" of their 3D SiP, which is the greatest hurdle to their design and production. Whether HBM dies are used on top of logic or multiple logic dies on top of each other (as is shown in their graphic), how can the heat of the low and middle layers be removed?
    Is this solely intended for very low power mobile SoCs, clocked at <1.5 GHz but ending up being faster than single die normally clocked ones due to the much higher transistor count? Or are they going to employ elaborate cooling between the dies based on microfluidics?
  • boeush - Friday, September 7, 2018 - link

    Microfluidics is one idea. An alternative might be to sandwich some heat-spreading layers in between those stacked dies - copper plates, or graphene, or something like that - to pipe the heat away into some overarching heatsink. But yeah, an interesting engineering challenge either way - and something I've been wondering about ever since Moore's Law began to sputter out in earnest.
  • Anymoore - Sunday, September 30, 2018 - link

    I just noticed on the capacity slide 7nm or under was not mentioned at all under any of the current fabs. 8nm was put under S1, which seems to be an older fab(?).

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