> I am very much looking forward to iWatch's with improved battery life, 2tb micro SDXC cards, whatever innovations may come from this new process node.
I'm afraid Apple Watch battery use (and other smart watches) are dominated by screen use and other activities, not the CPU which is inactive / sleeping 99+% of the time. It's more likely that the FDSOI technologies by GF would provide lower sleep power than the ultra performance nodes. Similarly, nonvolatile technologies like SSDs / SDXC are dominated by other things, like the capacitors for flash, and these high density / high performance transistors will not impact at all.
These transistors are 100% going to be used where ultra-density is what's important, and that means CPUs where the distance between transistors dominates the speed they can run at. Think smart phones, video games, PCs, servers, tablets.
what will be worth it, is that all sensors will be on lower nodes as well, as the legacy nodes are overbooked to hell and it will be worth it to make sensors on something like 80nm, because of the dedlines and waiting time on 2u or higher nodes. Power usage gains should be quite nice this gen. I still wait for solid state batteries which would make belts in those devices into 20x as big battery and would make those finally hold charge as long as their analog predecesors.
TSMC has finally hit a wall. N3 is delayed and yields are bad, hence why Apple wont use it for the iphone 14 this year. But instead will ship first with the tiny Intel Meteor Lake IGP dies in Q2 2023 or an iPad refresh in 2023. And now they are extending the N3 family through 2025. Just like they extended N5/N4 family because of the N3 issues. If Intel keeps their current pace and roadmap they will match TSMC in 2024 and surpass them in 2025.
Intel's execution has been so poor recently that their aggressive fab roadmap seems unrealistic to me. Intel 4 by 2023, Intel 3 by 2024, and Intel 20A/18A by 2024-2025 seems very aggressive. This is from a company that is currently struggling to deliver Alchemist (drivers?), Sapphire Rapids (memory controller? chiplets?) and Ponte Vecchio (chiplets?). Alder Lake was the only timely launch recently, and that is a monolithic die on a mature node...
Let's see if Intel can deliver, but I am somewhat doubtful....
I'm not going to comment on whether or not Intel hits their node roadmap, but Alchemist Drivers, SPR delays, and Ponte Vecchio issues are all unrelated, different departments/teams from nodes.
Intel's execution was very poor in the past because it was being run by stupid bean counters rather than real engineers (like in amd, nvidia, etc).
Now it's being run by a real engineer who knows about engineering silicon. And they're doing all the right things. If they deliver Intel 4 on time, the rest will be history. And it appears it's well on track.
Maybe I missed it, but I don't see the word "delayed" in this article. Or anything related to being unable to maintain their goals. I do see that getting to the smallest sizes is getting harder for them. But that's hardly a surprise, especially with many of the TwinScan EUV machines being delivered and installed late.
It's not delayed. TSMC is sticking to their timeline. TSMC only officially stayed a timeline in April 2020, and that was 22H2. There was a estimated risk production timeline in 2019 that shows N3 risk production around 2021-2022 time frame.
Bobby, what you are saying implies Intel sticking to its road map, which has Intel 4 appearing in Q3 '22 and Intel 3 in Q3'23. Forget Q3'22--what product is using intel 4 this at any time this year? What Intel product will be using intel 3 in 2023? These are both rhetorical questions, because nothing on Intel's CPU roadmap lines up with its foundry roadmap. Raptor lake (still 7) is Q4 this year (at best), and Meteor Lake (4) will be mid next year for just mobile parts (desktop well after that). While TSMC is having delays on 3nm, the key takeaway here is that Intel's road map is out of touch with actual products hitting the market. If intel wants the node lead, they have to meet their deadlines and have shown no ability to do so yet. If Intel gets their 20a node products into market prior to TSMC getting 2nm into market, then they may challenge TSMC for the lead and take it, but I have serious doubts about their ability to meet deadlines and to do so with strong yields as they have yet to accomplish that in the last 8 years.
TouchdoenTom9, Have you considered Intel 'fast follower' does not want the node lead on observing and learning and well, doing what Intel does keeping tabs on TSMC. Intel itself buffered into TSMC between 6 nm and 3 nm to monitor its own in-house progress v Intel designs at TSMC. Here's the economic reason for fast follower. As long as Intel trails TSMC by one node Intel is always on the downward sloping (depreciating) cost curve of the prior or lagging node as TSMC moves to the upward sloping cost curve of every next leading node. On this technique Intel cost is always going down as TSMC cost is going up. Think opposing low high sign wave. On leading, Intel's best chance to leap frog is advanced packaging and Intel would like to sell TSMC back end packaging between Chandler and Rio Rancho? I think so. mb
Intel's failure to maintain the lead in process technology was not intentional. They are currently behind because of execution failures, not because they planned to fall behind. If they successfully execute on their current road map (which, as techjunkie123 says, is quite aggressive), they may well regain the lead.
The economic benefits of being a fast follower are questionable. The “depreciating cost curve” is an accounting convention. Building a new fab (or upgrading an existing fab to use a new process) is an expensive proposition, and the money needs to be shelled out up front, before the fab generates any revenue. The accountants will amortize this cost over the expected life of the fab. The accountants expect the prices customers are willing to pay to drop over time as more fabs are built that support a similar or more advanced process. Therefore, they will allocate more of the cost of building the fab to chips manufactured early in the life of the fab, and less of the cost to chips manufactured later on.
What that means is that, if you build a fab, the cost of manufacturing a chip reported by the accountants will decrease over time. It does not mean that you can lower your costs simply by bringing a fab on line later. To decrease your costs, you actually have to decrease the cost of building the fab. Lagging behind your competitors does have the potential to decrease costs, both because there is the possibility that equipment manufactures will decrease their prices, and because competitors may reveal helpful information. I doubt that either of these are enough to make up for the opportunity cost of not being able to sell cutting edge products. There are large markets for processes that are well behind the state of the art, but being just marginally behind the state of the art means you are competing directly with people who are at the state of the art.
"Intel's failure to maintain the lead in process technology was not intentional. Execution Failure".
Hum? How about sabotage in a multipoint manipulation by internal and external gangs is my take on 1) industry actors taking law enforcement subject monopoly regulation into their own hands disgusted by 30 years of nonregulation, and 2) parallels $350 billion DCG hard cost loss associated Xeon product laundering theft would have paid for a lot of R&D and PC&E.
The economic benefits of fast follower I concur a short run benefit, technique, in relation long run cost : price / margin recovery of Capital Expenditure associated Plant, Construction, Equipment.
By simply cost optimizing Intel can return up to $23 billion a year to the bottom line. CFO Zinser has set a 30% cost reduction objective associated avoidable and unnecessary expenditure here are three from my view; 1) sales close incentive aka bundle deal freebie, 2) unnecessary soft marketing expenditures, 3) avoidable financial leaks and I'll be direct here; employees in cahoots with customer gang thefts.
By Intel closing its financial leaks, minimally + 30% revenue per year can be redirected to research, development, plant, construction and equipment and maintenance.
These are Intel's basic cost centers in 2021 on production of 391,800,000 components of all types; 221,800,00 Core products that is Gartner annual PC less my AMD all up at 118 M. In additional on my Intel data 70 M Xeon which into 2022 has currently halved. Plus 100 M control hubs, NICs, SSD memory controllers, possibly Atom supply sows a dead product line that Intel contracts to foundries.
If Intel sell for $39 or less contracted out and at $79 still within variable cost range is cost effective to contract out.
In 2021 average total cost = $306.76 per unit and to make a 55% gross margin Intel needs to charge $475.47 to OEM where $1K price would be $713.20 at x1.5 margin.
Intel needs to raise price by 135% and if Sapphire Rapids as a Xeon price support does that Intel will be in good shape. But if not and Sapphire Rapids stalls into q3, Intel declaring Chapter 11 isn't off the table and is among the options of any structural reconfiguration.
I don't believe SR is delated by the way solely hardware ahead of software specific what is whole (mass market) product beyond business of compute as a self sufficient whole platform developer.
Now let's consider PC&E cost is $63,245,000,000 in 2021, Intel depreciates physical infrastructure between 20 and 30 years and equipment over seven years which is two to two plus one-half process cycles and I think Intel 7, 4(5), 3, 2.8 and 1.8 is not five but 2.5 traditional lithography cycles, tick tock on the stretch of the lithography equipment. However, if it is not 2.5 cycles and ends up being 5 cycles that's costly and Intel isn't talking about the additional cost of advanced packaging.
Rocks Law doubles cost every process node to double transistors and let's keep that in mind, it's relevant but not in the way it once was, although, advanced packaging is costly and over the short run likely exceeds dice fabrication cost.
On PC&C brown and greenfield Intel plans to invest between Arizona build, Rio Rancho retrofit, Hillsboro retrofit, Leixlip retrofit, Ohio build and Europe build a total of $229,500,000,000.
Minimally straight lined out over 20 years the capital expenditure adds $21.354 billion per year through 2027 then drops to $12.8 billion in maintenance. This is obviously a simple way of looking at the impact of capital investment.
In 2021 PC&E increased on average 2% per quarter with q4 2021 up 11.7% from q4 2020. If Intel proceeds with all projects suggested, PC&E will increase from $63.245 billion to $84.6 billion and despite depreciation that cost never truly goes down for every depreciation credit debited to sustained maintenance.
At PC&E $84.6 billion, per unit cost charge gains from $161.41 to $214.83 and ATC is now $360.16 + 17.4% on the same unit volume as 2021 = 391.8 M where the idea is to produce more product maintaining efficiency of the manufacturing cost structure. Intel would have to increase production 33% to 521 M units to maintain PC&E at $161. 2020 I have Intel production at 500 M units that was mostly 14 nm run end.
On price situation 2021 is up over 2020 by 29.5% per unit at $155.73 to $201.69 and gross up $87.22 to $111.83 respectively Intel was in bad shape and no wonder Intel had to retool as DCG and Core lines hit variable cost hard in 2019 and 2020 respectively.
At 521 M units Intel annual revenue is $105 billion at constant $201.69 per unit but that price could increase dependent performance and competitive situation.
I expect on Rocks Law not a doubling, however PC&E cost line will approach $100 billion by the time Intel reaches 2.8A at which time PC&E per unit at 2021 volume will be $255.23 and ATC $400.57. To maintain PC&E at $161 per unit Intel will need to sell 620 M units for revenue value $125 billion and that's within 5 years.
That's a revenue increase at constant $201 per unit and fixed plus variable cost which will go up on manpower requirement by 58%. R&D will also increase and I'm not taking into account variable and R&D increases in these estimates.
To maintain the competitive price of $201.69 Intel top shelf margin will have to cover it as it does today and where down bin components represent a gross margin drag. By the time Intel PC&E doubles from 2022 at $84 billion to $168 billion per unit cost at the 2021 constant is $429 and to keep PC&E constant at $161 Intel will have to sell 1 billion units valued $209 billion. Intel is both an IDM and foundry by this time and Intel foundry will not be producing low priced components on the margin requirement. Legacy will be prior four to six process nodes and these will be premium products primarily.
In summary if Sapphire Rapids or any other Xeon for the needed price support fails or is rejected by the customer base, Intel declares bankruptcy remains one of the options.
If things take a turn for the worst in the next two years during fab construction, intuitively its the classic Intel to misrepresent the situation leading up to a failure and Intel will land themselves in Chapter 11, And on any partial fab construction site sitting their Intel would ask the government to assist in the completion of the project.
This is classic Intel reversing the obvious on some high hurdles to reconfigure the business from its nonorganic extra economic monopoly cost structure that is extraordinary impacted on the cost of corporate theft. Intel should already have these fabs developments built, productive and paid for.
Intel has publicly said they aspire for leadership and not to be a fast follower, go research Pat's ambitions!
They claim the IDM+Foundry is a competitive advantage. It is actually a flawed thinking as when you are an IDM your first priority is to fab your own designs in your own factory for advantage. All your competitors won't use you. Those that don't compete will always wonder and rightly so whether you prioritize your own internal designs over theirs. Foundry by definition is agnostic, not really, but they don't compete against their customers.
Running a trailing node as Intel is with 10nm and their intel 7 which really is 10 nm makes their internal products bigger, more power hunger and costlier than AMD, Nvidia, Apple and everyone else that has access to Foundry 5nm, 4nm and soon 3nm. Also they have the ability to leverage the foundry scale which means cheaper because bigger volume than Intel.
Your concept of depreciation is flawed. Intel has to depreciate their new tools regardless of lagging node or new node. Actually you can see this in the financials as margins are plummeting as they now are depreciating their expensive 10nm fabs. Foundry with their scale can depreciate across a far larger volume and they continue to run their fabs for many years at pure profit after they are depreciated. As and IDM Intel has to flip its fabs to leading edge as they have nothing to fill their older fabs and why they now are trying desperately to get into the Foundry space.
If you think the IDM model is superior look at the GM for the past few years of Foundry and considering adding the GM of their customers and compare with the total GM of Intel to see who has the better business model.
You should check on package, I don't think Intel is that superior than what is offered to the likes of Apple and AMD from Foundry space
"Running a trailing node as Intel is with 10nm and their intel 7 which really is 10 nm makes their internal products bigger, more power hunger and costlier than AMD, Nvidia, Apple and everyone else"
This isn't really accurate in terms of real world products. An Alder Lake i7-12700K is a monolithic 215 mm^2 square die. That's pretty close to the 206 mm^2 total die area of the Ryzen 5800X and substantially smaller than the 287 mm^2 die area of the 5900X.
That i7-12700K outperforms both Ryzen processors in both single-core and multi-core performance, and depending on the load (i.e. gaming) can even achieve superior performance per watt.
So it's clearly not accurate to characterize Intel 7 as "really a 10nm node" when it is competitive or superior to the TSMC N7 node that it is directly competing with today. Unless you want to argue that TSMC N7 is also "really a 10nm node." I guess that's fine, but an unnecessary semantic debate...
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Intel is using Intel 7 this year with new the HP library (v2). Might take raptor lake upto 6 GHz (with a slight increase in power draw). But will beat AMD by a mile in performance but not efficiency though.
Intel is going to use Intel 4 next year which is far superior to TSMC N5 & N4 that AMD uses. In fact, the Intel 4 HP library is actually slightly better than than even the upcoming TSMC N3.
Intel is going to use Intel 20A in 2024 for it's Arrow Lake and AMD will still be using the old TSMC N3 which is one *full* node behind. AMD is going to lag both in performance AND power efficiency. Intel now leads AMD in all aspects.
Intel is going to use Intel 18A in 2025 for next gen client cpus while AMD will still be stuck in the old TSMC N3 which will now be *TWO FULL NODES* behind. Henceforth, AMD will be history.
Intel's execution woes will be over once they launch Intel 4. And its going into risk production this Q4 and volume ramp in Q2 2023.
As a contingency measure, they've also secured major N3 capacity starting 2023 & their client dies are now fully node agnostic starting 2023. They can jump to N3 anytime they wish if 20A falls behind. There no stopping Intel anymore.
That's from nearly 2 years ago. And I'm sure earlier reports have mentioned the same timeline.
TSMC's FinFET processes have always entered HVM during Q2 and start producing Apple chips no later than early June. The earliest for N3 to actually enter mass production is August 2022 for 22H2 schedule. Why do you think Apple could possibly choose N3 and keep September/October shipping date? It's obviously not planned. Not delayed.
If Intel keeps their current pace of updating their roadmaps and releasing marketing materials then poor TSMC will have no choice but to expand production and gain market share.
The only real threat to TSMC is that their giant honey pot might attract the attention of a malevolent Pooh bear.
Looking at the timing N3 looks to be on time or close enough within a margin of error. Maybe not what Apple wants but on time from a TSMC perspective. What does look delayed is N2.
Intel's roadmap is indeed impressive; however, 2 things give me pause.
First, as techjunkie123 points out, Intel hasn't exactly been a shining beacon of execution in process technology lately (14nm +++++ anyone?).
Second, if you look carefully at both TSMC and Intel's roadmaps, they are both essentially talking about a couple really big things in the next 5 years. Gate All Around (a better implementation of multiple fins in finfets ... which I guess now we will call GalaFets? Intel likes to call it ribbon FET), and EUV (which TSMC is already doing with its N7+ and N5 nodes).
Both companies are using ASML equipment for EUV. I wouldn't bet the farm on intel out-executing TSMC in the near future IMO.
TSMCs international fabs will be enough to keep militaries going in a fight against west Taiwan, but it will not be anywhere close to meeting civilian needs.
We all will be stuck defending Taiwan from its grumpy neighbor for at least a decade to come.
Samsung, Intel, GlobalFoundries, and others have fabs. I don't think TSMC is planning to stop building new fabs in Taiwan, but they are at least putting some more overseas.
The U.S. seems to be ready to throw money at the problem, and we could see something interesting come out of the SkyWater-DARPA partnership.
At some point, scaling will stop and it will all be moot. Advanced fabs will catch up with each other and others will stay in their lane on older nodes more suitable for some applications.
yea, but throwing money at the problem does not catch us up to TSMC. The real value in TSMC is the people, and it will take a sustained effort for many years to develop the talent to compete.
I do not think anyone expects anyone else to catch up to TSMC for at least a decade. It it not just the high end nodes either, TSMC cranks out a massive number of chips across all of its nodes.
TSMC is in everything from cars to microwaves. It is not just a matter of catching up with their high end nodes, it is matter of catching up to their massive volume.
Leeea, good point TSMC massive volume, "it is a matter of massive volume".
I have not calculated TSMC component volume but will make that attempt. I am aware of Intel's 321 M in house + 100 M contract now moving to 521 M capable, moving to 621 M total by 2.8A and by the time Intel doubles PC&E cost line on CapEx would require 1 B units a year to sustain today's PC&E cost line at $162 per component produced. Also note Intel variable cost range $39 to $79 dependent on product line and range high $107ish is when Intel products get contracted out to foundries. Anything priced to the customer < variable cost.
TSMC average process density can be calculated and its 12 nm determined on the averages percent node contribution from 250 down to 5 nm. TSMC reports 13 M wafers annual. 53,000 mm2 that is an 75% yield means 698,000,000,000 mm^2 area of good silicon.
I don't have the data to state an average component area but will throw out Nvidia at 457 mm2, AMD dGPU at 411 mm2, AMD 7 nm CPU all up at 245 mm2, Intel I don't have a normalized currently lets just say Intel is competitive with AMD my quick % Xeon, Desktop, Mobile production around 230 and Intel likes 240 to 260 mm2 the quick average is 290.
TSMC average at half on all embedded say 150 mm2 average = 4.590 B TSMC components. Lets go to 100 mm2 corporations like round numbers = 6.890 B. And if all the little 25 mm2 embedded components say 75 mm2 average now = 9.186 B. The nice round number is TSMC at 10 billion components annual.
The scale and breadth across leading edge as well as legacy node at TSMC is a huge competitive advantage as well as fundamental anchor for the value of a foundry relationship to its customer.
Intel has flawed believe that it can selectively pick foundry offering based on excessive capacity. One that capacity won't be trusted nor believed stable by potential customers. That alone will be a fundamental issue. Of course everyone will say they will use it, Nvidia, to get price leverage against their real supplier
"With TSMC FINFLEX™ in N3, product designers can choose the best FIN configuration for each of these functional blocks, optimizing each block without affecting others, all on the same die"
sounds amazing, even withouth using chiplets technology
I would be very interested to know what was stopping product designers from mixing 2-1, 2-2 and 3-2 libraries previously: is it some kind of uniformity issue at the transistor level, where you want substantial blocks with the same 'texture' of gates and fins to avoid optical or measurement problems at intermediate spatial frequencies larger than transistors but smaller than SoC blocks.
Chiplets & tiles give full abstraction. Meaning, completely different engineering teams can work on their own tiles without any intervention from others. Theoretically.
Also, they can mix & match tiles (IP) at will. FINFLEX doesn't allow that. Just optimizes & enhances performance and power efficiency of a big monolithic die.
The real advantage is, if they can put FINFLEX into independent chiplets or tiles. But i don't think anyone wud choose to do that cos it makes the chiplet node or process dependent. Not worth the effort.
So they are basically doing what Intel did for 14nm and 10nm. Yeah it's known that as the size decreases the complexity and cost rises sharply. Makes sense.
AMD and Intel are the only ones when I see these lithography processes. ARM smartphone trash is basically useless after a year or max 3 years (stretching thin). So looking at AMD's details and TSMC, it's very clear on Node jumps are not going to be rapid. Thanks. Else I was getting tired of Apple's BS marketing nonsense.
Back to HW, AMD's Zen 5 is on 4nm, it's 2024-2025. So the N3 is not even relevant here, I bet it's more for a Smartphone node or Low Power one so Zen5 BGA junk. I wonder what RDNA4 and Nvidia Blackwell will be on, TSMC N3's high performance maybe, that's anyways post 2025.
So the biggest changes are going to come in 2025, Intel must move out of Intel 4, and go to 18A node and abandon their CORE design. AMD on the other hand will debut Zen 5 and up plans, Next Next Gen GPUs.
Samsung GAAFET, TSMC Nanosheet, Intel's RibbonFET are going to be the next high tech advancements.
So as of today highest volume is Intel 14nm is phased out slowly, Intel 7 or Intel 10nm replacing it by a huge margin, TSMC 7N+5N both (AMD and Nvidia GPUs plus AMD processors), even Apple's BGA on N5.
By 2025 maybe Intel 4 will take the spot for them, Samsung no idea honestly. TSMC N3.
I don't think Intel ever gave it a fancy marketing moniker like 'flexfin', but back when 10nm got its deep-dive in 2018 one of the features (in amongst all the other stuff that was crammed in the at the same time) was that all three transistor libraries libraries could add/remove one fin per transistor (as long as they were in the same poly line, because SAQP) in addition to regional library changes.
ibraries or transistor --> libraries or transistor largest contrast maker --> largest contract maker Figure shows FinFlex for N3E: is it on purpose or just an example? What about memory density reductions? And N2? Any info/rumors on those?
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Rictorhell - Thursday, June 16, 2022 - link
I am very much looking forward to iWatch's with improved battery life, 2tb micro SDXC cards, whatever innovations may come from this new process node.chrysrobyn - Thursday, June 16, 2022 - link
> I am very much looking forward to iWatch's with improved battery life, 2tb micro SDXC cards, whatever innovations may come from this new process node.I'm afraid Apple Watch battery use (and other smart watches) are dominated by screen use and other activities, not the CPU which is inactive / sleeping 99+% of the time. It's more likely that the FDSOI technologies by GF would provide lower sleep power than the ultra performance nodes. Similarly, nonvolatile technologies like SSDs / SDXC are dominated by other things, like the capacitors for flash, and these high density / high performance transistors will not impact at all.
These transistors are 100% going to be used where ultra-density is what's important, and that means CPUs where the distance between transistors dominates the speed they can run at. Think smart phones, video games, PCs, servers, tablets.
deil - Monday, June 20, 2022 - link
what will be worth it, is that all sensors will be on lower nodes as well, as the legacy nodes are overbooked to hell and it will be worth it to make sensors on something like 80nm, because of the dedlines and waiting time on 2u or higher nodes. Power usage gains should be quite nice this gen.I still wait for solid state batteries which would make belts in those devices into 20x as big battery and would make those finally hold charge as long as their analog predecesors.
Bobbyjones - Thursday, June 16, 2022 - link
TSMC has finally hit a wall. N3 is delayed and yields are bad, hence why Apple wont use it for the iphone 14 this year. But instead will ship first with the tiny Intel Meteor Lake IGP dies in Q2 2023 or an iPad refresh in 2023. And now they are extending the N3 family through 2025. Just like they extended N5/N4 family because of the N3 issues. If Intel keeps their current pace and roadmap they will match TSMC in 2024 and surpass them in 2025.techjunkie123 - Thursday, June 16, 2022 - link
Intel's execution has been so poor recently that their aggressive fab roadmap seems unrealistic to me. Intel 4 by 2023, Intel 3 by 2024, and Intel 20A/18A by 2024-2025 seems very aggressive. This is from a company that is currently struggling to deliver Alchemist (drivers?), Sapphire Rapids (memory controller? chiplets?) and Ponte Vecchio (chiplets?). Alder Lake was the only timely launch recently, and that is a monolithic die on a mature node...Let's see if Intel can deliver, but I am somewhat doubtful....
kwohlt - Sunday, June 19, 2022 - link
I'm not going to comment on whether or not Intel hits their node roadmap, but Alchemist Drivers, SPR delays, and Ponte Vecchio issues are all unrelated, different departments/teams from nodes.SiliconFly - Sunday, June 26, 2022 - link
Intel's execution was very poor in the past because it was being run by stupid bean counters rather than real engineers (like in amd, nvidia, etc).Now it's being run by a real engineer who knows about engineering silicon. And they're doing all the right things. If they deliver Intel 4 on time, the rest will be history. And it appears it's well on track.
ballsystemlord - Thursday, June 16, 2022 - link
Maybe I missed it, but I don't see the word "delayed" in this article. Or anything related to being unable to maintain their goals.I do see that getting to the smallest sizes is getting harder for them. But that's hardly a surprise, especially with many of the TwinScan EUV machines being delivered and installed late.
dotjaz - Friday, June 17, 2022 - link
It's not delayed. TSMC is sticking to their timeline. TSMC only officially stayed a timeline in April 2020, and that was 22H2. There was a estimated risk production timeline in 2019 that shows N3 risk production around 2021-2022 time frame.http://www.gizmochina.com/2020/04/17/tsmc-3nm-proc...
TouchdownTom9 - Thursday, June 16, 2022 - link
Bobby, what you are saying implies Intel sticking to its road map, which has Intel 4 appearing in Q3 '22 and Intel 3 in Q3'23. Forget Q3'22--what product is using intel 4 this at any time this year? What Intel product will be using intel 3 in 2023? These are both rhetorical questions, because nothing on Intel's CPU roadmap lines up with its foundry roadmap. Raptor lake (still 7) is Q4 this year (at best), and Meteor Lake (4) will be mid next year for just mobile parts (desktop well after that). While TSMC is having delays on 3nm, the key takeaway here is that Intel's road map is out of touch with actual products hitting the market. If intel wants the node lead, they have to meet their deadlines and have shown no ability to do so yet. If Intel gets their 20a node products into market prior to TSMC getting 2nm into market, then they may challenge TSMC for the lead and take it, but I have serious doubts about their ability to meet deadlines and to do so with strong yields as they have yet to accomplish that in the last 8 years.Bruzzone - Friday, June 17, 2022 - link
TouchdoenTom9, Have you considered Intel 'fast follower' does not want the node lead on observing and learning and well, doing what Intel does keeping tabs on TSMC. Intel itself buffered into TSMC between 6 nm and 3 nm to monitor its own in-house progress v Intel designs at TSMC. Here's the economic reason for fast follower. As long as Intel trails TSMC by one node Intel is always on the downward sloping (depreciating) cost curve of the prior or lagging node as TSMC moves to the upward sloping cost curve of every next leading node. On this technique Intel cost is always going down as TSMC cost is going up. Think opposing low high sign wave. On leading, Intel's best chance to leap frog is advanced packaging and Intel would like to sell TSMC back end packaging between Chandler and Rio Rancho? I think so. mbKAlmquist - Friday, June 17, 2022 - link
Intel's failure to maintain the lead in process technology was not intentional. They are currently behind because of execution failures, not because they planned to fall behind. If they successfully execute on their current road map (which, as techjunkie123 says, is quite aggressive), they may well regain the lead.The economic benefits of being a fast follower are questionable. The “depreciating cost curve” is an accounting convention. Building a new fab (or upgrading an existing fab to use a new process) is an expensive proposition, and the money needs to be shelled out up front, before the fab generates any revenue. The accountants will amortize this cost over the expected life of the fab. The accountants expect the prices customers are willing to pay to drop over time as more fabs are built that support a similar or more advanced process. Therefore, they will allocate more of the cost of building the fab to chips manufactured early in the life of the fab, and less of the cost to chips manufactured later on.
What that means is that, if you build a fab, the cost of manufacturing a chip reported by the accountants will decrease over time. It does not mean that you can lower your costs simply by bringing a fab on line later. To decrease your costs, you actually have to decrease the cost of building the fab. Lagging behind your competitors does have the potential to decrease costs, both because there is the possibility that equipment manufactures will decrease their prices, and because competitors may reveal helpful information. I doubt that either of these are enough to make up for the opportunity cost of not being able to sell cutting edge products. There are large markets for processes that are well behind the state of the art, but being just marginally behind the state of the art means you are competing directly with people who are at the state of the art.
tyb60 - Friday, June 17, 2022 - link
Well said, and why their current strategy requires tens of billions of tax payer money as the model is flawed from the beginningkwohlt - Sunday, June 19, 2022 - link
Just pointing out that both Samsung and TSMC are heavily subsidizedBruzzone - Thursday, June 23, 2022 - link
KAlmquist,"Intel's failure to maintain the lead in process technology was not intentional. Execution Failure".
Hum? How about sabotage in a multipoint manipulation by internal and external gangs is my take on 1) industry actors taking law enforcement subject monopoly regulation into their own hands disgusted by 30 years of nonregulation, and 2) parallels $350 billion DCG hard cost loss associated Xeon product laundering theft would have paid for a lot of R&D and PC&E.
The economic benefits of fast follower I concur a short run benefit, technique, in relation long run cost : price / margin recovery of Capital Expenditure associated Plant, Construction, Equipment.
By simply cost optimizing Intel can return up to $23 billion a year to the bottom line. CFO Zinser has set a 30% cost reduction objective associated avoidable and unnecessary expenditure here are three from my view; 1) sales close incentive aka bundle deal freebie, 2) unnecessary soft marketing expenditures, 3) avoidable financial leaks and I'll be direct here; employees in cahoots with customer gang thefts.
By Intel closing its financial leaks, minimally + 30% revenue per year can be redirected to research, development, plant, construction and equipment and maintenance.
These are Intel's basic cost centers in 2021 on production of 391,800,000 components of all types; 221,800,00 Core products that is Gartner annual PC less my AMD all up at 118 M. In additional on my Intel data 70 M Xeon which into 2022 has currently halved. Plus 100 M control hubs, NICs, SSD memory controllers, possibly Atom supply sows a dead product line that Intel contracts to foundries.
If Intel sell for $39 or less contracted out and at $79 still within variable cost range is cost effective to contract out.
In 2021 average total cost = $306.76 per unit and to make a 55% gross margin Intel needs to charge $475.47 to OEM where $1K price would be $713.20 at x1.5 margin.
Intel needs to raise price by 135% and if Sapphire Rapids as a Xeon price support does that Intel will be in good shape. But if not and Sapphire Rapids stalls into q3, Intel declaring Chapter 11 isn't off the table and is among the options of any structural reconfiguration.
I don't believe SR is delated by the way solely hardware ahead of software specific what is whole (mass market) product beyond business of compute as a self sufficient whole platform developer.
Now let's consider PC&E cost is $63,245,000,000 in 2021, Intel depreciates physical infrastructure between 20 and 30 years and equipment over seven years which is two to two plus one-half process cycles and I think Intel 7, 4(5), 3, 2.8 and 1.8 is not five but 2.5 traditional lithography cycles, tick tock on the stretch of the lithography equipment. However, if it is not 2.5 cycles and ends up being 5 cycles that's costly and Intel isn't talking about the additional cost of advanced packaging.
Rocks Law doubles cost every process node to double transistors and let's keep that in mind, it's relevant but not in the way it once was, although, advanced packaging is costly and over the short run likely exceeds dice fabrication cost.
On PC&C brown and greenfield Intel plans to invest between Arizona build, Rio Rancho retrofit, Hillsboro retrofit, Leixlip retrofit, Ohio build and Europe build a total of $229,500,000,000.
Minimally straight lined out over 20 years the capital expenditure adds $21.354 billion per year through 2027 then drops to $12.8 billion in maintenance. This is obviously a simple way of looking at the impact of capital investment.
In 2021 PC&E increased on average 2% per quarter with q4 2021 up 11.7% from q4 2020. If Intel proceeds with all projects suggested, PC&E will increase from $63.245 billion to $84.6 billion and despite depreciation that cost never truly goes down for every depreciation credit debited to sustained maintenance.
At PC&E $84.6 billion, per unit cost charge gains from $161.41 to $214.83 and ATC is now $360.16 + 17.4% on the same unit volume as 2021 = 391.8 M where the idea is to produce more product maintaining efficiency of the manufacturing cost structure. Intel would have to increase production 33% to 521 M units to maintain PC&E at $161. 2020 I have Intel production at 500 M units that was mostly 14 nm run end.
On price situation 2021 is up over 2020 by 29.5% per unit at $155.73 to $201.69 and gross up $87.22 to $111.83 respectively Intel was in bad shape and no wonder Intel had to retool as DCG and Core lines hit variable cost hard in 2019 and 2020 respectively.
At 521 M units Intel annual revenue is $105 billion at constant $201.69 per unit but that price could increase dependent performance and competitive situation.
I expect on Rocks Law not a doubling, however PC&E cost line will approach $100 billion by the time Intel reaches 2.8A at which time PC&E per unit at 2021 volume will be $255.23 and ATC $400.57. To maintain PC&E at $161 per unit Intel will need to sell 620 M units for revenue value $125 billion and that's within 5 years.
That's a revenue increase at constant $201 per unit and fixed plus variable cost which will go up on manpower requirement by 58%. R&D will also increase and I'm not taking into account variable and R&D increases in these estimates.
To maintain the competitive price of $201.69 Intel top shelf margin will have to cover it as it does today and where down bin components represent a gross margin drag. By the time Intel PC&E doubles from 2022 at $84 billion to $168 billion per unit cost at the 2021 constant is $429 and to keep PC&E constant at $161 Intel will have to sell 1 billion units valued $209 billion. Intel is both an IDM and foundry by this time and Intel foundry will not be producing low priced components on the margin requirement. Legacy will be prior four to six process nodes and these will be premium products primarily.
In summary if Sapphire Rapids or any other Xeon for the needed price support fails or is rejected by the customer base, Intel declares bankruptcy remains one of the options.
If things take a turn for the worst in the next two years during fab construction, intuitively its the classic Intel to misrepresent the situation leading up to a failure and Intel will land themselves in Chapter 11, And on any partial fab construction site sitting their Intel would ask the government to assist in the completion of the project.
This is classic Intel reversing the obvious on some high hurdles to reconfigure the business from its nonorganic extra economic monopoly cost structure that is extraordinary impacted on the cost of corporate theft. Intel should already have these fabs developments built, productive and paid for.
Mike Bruzzone, Camp Marketing.
tyb60 - Friday, June 17, 2022 - link
Intel has publicly said they aspire for leadership and not to be a fast follower, go research Pat's ambitions!They claim the IDM+Foundry is a competitive advantage. It is actually a flawed thinking as when you are an IDM your first priority is to fab your own designs in your own factory for advantage. All your competitors won't use you. Those that don't compete will always wonder and rightly so whether you prioritize your own internal designs over theirs. Foundry by definition is agnostic, not really, but they don't compete against their customers.
Running a trailing node as Intel is with 10nm and their intel 7 which really is 10 nm makes their internal products bigger, more power hunger and costlier than AMD, Nvidia, Apple and everyone else that has access to Foundry 5nm, 4nm and soon 3nm. Also they have the ability to leverage the foundry scale which means cheaper because bigger volume than Intel.
Your concept of depreciation is flawed. Intel has to depreciate their new tools regardless of lagging node or new node. Actually you can see this in the financials as margins are plummeting as they now are depreciating their expensive 10nm fabs. Foundry with their scale can depreciate across a far larger volume and they continue to run their fabs for many years at pure profit after they are depreciated. As and IDM Intel has to flip its fabs to leading edge as they have nothing to fill their older fabs and why they now are trying desperately to get into the Foundry space.
If you think the IDM model is superior look at the GM for the past few years of Foundry and considering adding the GM of their customers and compare with the total GM of Intel to see who has the better business model.
You should check on package, I don't think Intel is that superior than what is offered to the likes of Apple and AMD from Foundry space
Turbofrog - Wednesday, June 22, 2022 - link
"Running a trailing node as Intel is with 10nm and their intel 7 which really is 10 nm makes their internal products bigger, more power hunger and costlier than AMD, Nvidia, Apple and everyone else"This isn't really accurate in terms of real world products. An Alder Lake i7-12700K is a monolithic 215 mm^2 square die. That's pretty close to the 206 mm^2 total die area of the Ryzen 5800X and substantially smaller than the 287 mm^2 die area of the 5900X.
That i7-12700K outperforms both Ryzen processors in both single-core and multi-core performance, and depending on the load (i.e. gaming) can even achieve superior performance per watt.
So it's clearly not accurate to characterize Intel 7 as "really a 10nm node" when it is competitive or superior to the TSMC N7 node that it is directly competing with today. Unless you want to argue that TSMC N7 is also "really a 10nm node." I guess that's fine, but an unnecessary semantic debate...
Bruzzone - Friday, June 17, 2022 - link
TdT9, Interesting point on Intel process and product road map alignment. mba668g - Monday, June 20, 2022 - link
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a668g - Monday, June 20, 2022 - link
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SiliconFly - Sunday, June 26, 2022 - link
Intel is using Intel 7 this year with new the HP library (v2). Might take raptor lake upto 6 GHz (with a slight increase in power draw). But will beat AMD by a mile in performance but not efficiency though.Intel is going to use Intel 4 next year which is far superior to TSMC N5 & N4 that AMD uses. In fact, the Intel 4 HP library is actually slightly better than than even the upcoming TSMC N3.
Intel is going to use Intel 20A in 2024 for it's Arrow Lake and AMD will still be using the old TSMC N3 which is one *full* node behind. AMD is going to lag both in performance AND power efficiency. Intel now leads AMD in all aspects.
Intel is going to use Intel 18A in 2025 for next gen client cpus while AMD will still be stuck in the old TSMC N3 which will now be *TWO FULL NODES* behind. Henceforth, AMD will be history.
Intel's execution woes will be over once they launch Intel 4. And its going into risk production this Q4 and volume ramp in Q2 2023.
As a contingency measure, they've also secured major N3 capacity starting 2023 & their client dies are now fully node agnostic starting 2023. They can jump to N3 anytime they wish if 20A falls behind. There no stopping Intel anymore.
dotjaz - Friday, June 17, 2022 - link
How is N3 delayed? It has always been 22H2 and unable to meet Apple's iPhone release cycle. We've known this since before 2020.dotjaz - Friday, June 17, 2022 - link
https://www.anandtech.com/show/16024/tsmc-details-...That's from nearly 2 years ago. And I'm sure earlier reports have mentioned the same timeline.
TSMC's FinFET processes have always entered HVM during Q2 and start producing Apple chips no later than early June. The earliest for N3 to actually enter mass production is August 2022 for 22H2 schedule. Why do you think Apple could possibly choose N3 and keep September/October shipping date? It's obviously not planned. Not delayed.
Blastdoor - Saturday, June 18, 2022 - link
If Intel keeps their current pace of updating their roadmaps and releasing marketing materials then poor TSMC will have no choice but to expand production and gain market share.The only real threat to TSMC is that their giant honey pot might attract the attention of a malevolent Pooh bear.
FreckledTrout - Thursday, June 23, 2022 - link
Looking at the timing N3 looks to be on time or close enough within a margin of error. Maybe not what Apple wants but on time from a TSMC perspective. What does look delayed is N2.OneEng - Monday, July 4, 2022 - link
Intel's roadmap is indeed impressive; however, 2 things give me pause.First, as techjunkie123 points out, Intel hasn't exactly been a shining beacon of execution in process technology lately (14nm +++++ anyone?).
Second, if you look carefully at both TSMC and Intel's roadmaps, they are both essentially talking about a couple really big things in the next 5 years. Gate All Around (a better implementation of multiple fins in finfets ... which I guess now we will call GalaFets? Intel likes to call it ribbon FET), and EUV (which TSMC is already doing with its N7+ and N5 nodes).
Both companies are using ASML equipment for EUV. I wouldn't bet the farm on intel out-executing TSMC in the near future IMO.
shabby - Thursday, June 16, 2022 - link
Is tsmc also expanding its fab location portfolio... as in adding fabs outside of taiwan incase west taiwan gets all pissy?Leeea - Thursday, June 16, 2022 - link
Yes, but not enough to matter.TSMCs international fabs will be enough to keep militaries going in a fight against west Taiwan, but it will not be anywhere close to meeting civilian needs.
We all will be stuck defending Taiwan from its grumpy neighbor for at least a decade to come.
nandnandnand - Thursday, June 16, 2022 - link
Samsung, Intel, GlobalFoundries, and others have fabs. I don't think TSMC is planning to stop building new fabs in Taiwan, but they are at least putting some more overseas.The U.S. seems to be ready to throw money at the problem, and we could see something interesting come out of the SkyWater-DARPA partnership.
At some point, scaling will stop and it will all be moot. Advanced fabs will catch up with each other and others will stay in their lane on older nodes more suitable for some applications.
Leeea - Friday, June 17, 2022 - link
yea, but throwing money at the problem does not catch us up to TSMC. The real value in TSMC is the people, and it will take a sustained effort for many years to develop the talent to compete.I do not think anyone expects anyone else to catch up to TSMC for at least a decade. It it not just the high end nodes either, TSMC cranks out a massive number of chips across all of its nodes.
TSMC is in everything from cars to microwaves. It is not just a matter of catching up with their high end nodes, it is matter of catching up to their massive volume.
dotjaz - Friday, June 17, 2022 - link
It's not like Samsung and Intel are far behind anyway. Worst case scenario Samsung and Intel can still produce something from last year.For example N4 isn't that much more advanced than Samsung's 4LPE. 10-15% better. Qualcomm never used this node. They renamed 5LPP to 4LPX.
Bruzzone - Friday, June 17, 2022 - link
Leeea, good point TSMC massive volume, "it is a matter of massive volume".I have not calculated TSMC component volume but will make that attempt. I am aware of Intel's 321 M in house + 100 M contract now moving to 521 M capable, moving to 621 M total by 2.8A and by the time Intel doubles PC&E cost line on CapEx would require 1 B units a year to sustain today's PC&E cost line at $162 per component produced. Also note Intel variable cost range $39 to $79 dependent on product line and range high $107ish is when Intel products get contracted out to foundries. Anything priced to the customer < variable cost.
TSMC average process density can be calculated and its 12 nm determined on the averages percent node contribution from 250 down to 5 nm. TSMC reports 13 M wafers annual. 53,000 mm2 that is an 75% yield means 698,000,000,000 mm^2 area of good silicon.
I don't have the data to state an average component area but will throw out Nvidia at 457 mm2, AMD dGPU at 411 mm2, AMD 7 nm CPU all up at 245 mm2, Intel I don't have a normalized currently lets just say Intel is competitive with AMD my quick % Xeon, Desktop, Mobile production around 230 and Intel likes 240 to 260 mm2 the quick average is 290.
TSMC average at half on all embedded say 150 mm2 average = 4.590 B TSMC components. Lets go to 100 mm2 corporations like round numbers = 6.890 B. And if all the little 25 mm2 embedded components say 75 mm2 average now = 9.186 B. The nice round number is TSMC at 10 billion components annual.
mb
tyb60 - Friday, June 17, 2022 - link
The scale and breadth across leading edge as well as legacy node at TSMC is a huge competitive advantage as well as fundamental anchor for the value of a foundry relationship to its customer.Intel has flawed believe that it can selectively pick foundry offering based on excessive capacity. One that capacity won't be trusted nor believed stable by potential customers. That alone will be a fundamental issue. Of course everyone will say they will use it, Nvidia, to get price leverage against their real supplier
Leeea - Thursday, June 16, 2022 - link
"the world's largest contrast maker of semiconductors"You mean largest contract maker of semiconductors?
del42sa - Friday, June 17, 2022 - link
"With TSMC FINFLEX™ in N3, product designers can choose the best FINconfiguration for each of these functional blocks, optimizing each block
without affecting others, all on the same die"
sounds amazing, even withouth using chiplets technology
TomWomack - Friday, June 17, 2022 - link
I would be very interested to know what was stopping product designers from mixing 2-1, 2-2 and 3-2 libraries previously: is it some kind of uniformity issue at the transistor level, where you want substantial blocks with the same 'texture' of gates and fins to avoid optical or measurement problems at intermediate spatial frequencies larger than transistors but smaller than SoC blocks.SiliconFly - Sunday, June 26, 2022 - link
FINFLEX is poor man's chiplet.Chiplets & tiles give full abstraction. Meaning, completely different engineering teams can work on their own tiles without any intervention from others. Theoretically.
Also, they can mix & match tiles (IP) at will. FINFLEX doesn't allow that. Just optimizes & enhances performance and power efficiency of a big monolithic die.
The real advantage is, if they can put FINFLEX into independent chiplets or tiles. But i don't think anyone wud choose to do that cos it makes the chiplet node or process dependent. Not worth the effort.
Silver5urfer - Friday, June 17, 2022 - link
So they are basically doing what Intel did for 14nm and 10nm. Yeah it's known that as the size decreases the complexity and cost rises sharply. Makes sense.AMD and Intel are the only ones when I see these lithography processes. ARM smartphone trash is basically useless after a year or max 3 years (stretching thin). So looking at AMD's details and TSMC, it's very clear on Node jumps are not going to be rapid. Thanks. Else I was getting tired of Apple's BS marketing nonsense.
Back to HW, AMD's Zen 5 is on 4nm, it's 2024-2025. So the N3 is not even relevant here, I bet it's more for a Smartphone node or Low Power one so Zen5 BGA junk. I wonder what RDNA4 and Nvidia Blackwell will be on, TSMC N3's high performance maybe, that's anyways post 2025.
So the biggest changes are going to come in 2025, Intel must move out of Intel 4, and go to 18A node and abandon their CORE design. AMD on the other hand will debut Zen 5 and up plans, Next Next Gen GPUs.
Samsung GAAFET, TSMC Nanosheet, Intel's RibbonFET are going to be the next high tech advancements.
So as of today highest volume is Intel 14nm is phased out slowly, Intel 7 or Intel 10nm replacing it by a huge margin, TSMC 7N+5N both (AMD and Nvidia GPUs plus AMD processors), even Apple's BGA on N5.
By 2025 maybe Intel 4 will take the spot for them, Samsung no idea honestly. TSMC N3.
edzieba - Friday, June 17, 2022 - link
I don't think Intel ever gave it a fancy marketing moniker like 'flexfin', but back when 10nm got its deep-dive in 2018 one of the features (in amongst all the other stuff that was crammed in the at the same time) was that all three transistor libraries libraries could add/remove one fin per transistor (as long as they were in the same poly line, because SAQP) in addition to regional library changes.ET - Saturday, June 18, 2022 - link
"FinFET-based noses"nandnandnand - Saturday, June 18, 2022 - link
"Angry FinFET noises"boletosexpress - Friday, June 24, 2022 - link
<a href="https://www.boletosexpress.com/alex-zurdo--cales-l...mef - Monday, August 1, 2022 - link
ibraries or transistor --> libraries or transistorlargest contrast maker --> largest contract maker
Figure shows FinFlex for N3E: is it on purpose or just an example?
What about memory density reductions? And N2? Any info/rumors on those?