Micron this week has announced that it has started sampling the industry’s first multichip package (MCP) that integrates LPDDR5-6400 DRAM and 96-layer 3D NAND flash memory. The uMCP5 device is aimed at midrange 5G smartphones that require fast DRAM as well as high-performance storage.

Micron’s uMCP5 device packs 12 GB of LPDDR5-6400 memory in a dual-channel arrangement, 256 GB of 96-layer 3D TLC NAND storage with a UFS interface, as well as an onboard controller. The LPDDR5 dies are made on the company's 2nd Generation 10nm process technology, while the company hasn't commented on the NAND. Combined, the complete uMCP5 chip uses a 297-pin standard BGA package.

Overall, uMCP packages that integrate both DRAM and 3D NAND enable smartphone manufacturers to reduce the footprint that is needed for RAM and storage. Micron says that its uMCP5 uses 40% less space than two (separate) memory chips, while also providing a 50% increase of memory and storage bandwidth when compared to previous-generation solutions.

All told, Micron's latest uMCP devices come as demand for LPDDR5 is taking off, and demand for higher performance storage overall is booming. On top of 5G's faster speeds putting more demand on quick local storage, the latest handsets in general feature increasingly better cameras and displays than predecessors, all of which generates more data to load and store. So there's a need for faster memory and non-volatile storage, not only for 5G smartphones, but higher-end 4G/LTE smartphones as well.

Micron’s uMCP5 package is currently sampling to select partners.

Related Reading:

Source: Micron

Comments Locked


View All Comments

  • faiakes - Wednesday, March 11, 2020 - link

    How is this midrange?
  • Ryan Smith - Wednesday, March 11, 2020 - link

    High-end phones tend to utilize SoCs with their RAM on-package in a PoP fashion. Off-package RAM is more of a midrange phone design choice.
  • name99 - Wednesday, March 11, 2020 - link

    Here's an example of what Ryan is talking about:

    Note how the DRAM sits directly on top of the SoC, forming a single package. The packaging is more expensive, but the end result is both a smaller volume (so a smaller phone) and that accessing the DRAM uses less energy because the wiring from SoC to DRAM is shorter and thinner.
  • ikjadoon - Wednesday, March 11, 2020 - link

    Is the three-stack PoP a connectivity problem or a thermal problem?

    What's holding back an SoC + DRAM + NAND on a single package?
  • PeachNCream - Thursday, March 12, 2020 - link

    Both, but by far thermals are more of a concern. The SoC is a source of significant heat it needs to dissapate rapidly, but passively in a mobile handset in order to maintain higher clocks under sustained workloads. NAND is thermally sensitive to the extent that higher temps mean shorter useful lifespan and the potential to lose previously saved data. Throwing another layer on a PoP that includes NAND would insulate the SoC and expose the NAND to additional heat.
  • Diogene7 - Friday, March 13, 2020 - link

    @PeachNCream: Thanks for this clarification : it is very interesting to know as I was also wondering why there still doesn’t exist PoP with an SoC + RAM memory (DRAM) + storage (Nand).

    I am wandering if any of the future Storage Class Memory (SCM) like (STT-)MRAM, Nantero Nanotube RAM (NRAM), ReRAM,... could help in getting a 3-in-one PoP or 3D-IC with compute + memory + storage toward 2023 / 2025 ? Or would we need to wait even longer than that ?
  • Small Bison - Wednesday, March 11, 2020 - link

    Does dual channel here mean two 32-bit channels?
  • steve wilson - Thursday, March 12, 2020 - link

    Hi Ryan,
    Is there any news on when DDR5 will be released for PC?
  • Ryan Smith - Thursday, March 12, 2020 - link

    That's more of an Ian question. But normally we'll see something like that show up in servers first.
  • RSAUser - Thursday, March 12, 2020 - link

    Sampling just started in Jan, you won't see it mass released for consumers till 2021 probably.
    Consumer side it doesn't really matter, Ddr5 will be a minor power consumption reduction for typical use cases, servers that are bandwidth starved it might matter.

Log in

Don't have an account? Sign up now